JPS63102349A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the space that a cell-checking circuit occupies in a device wiring region and to shorten the time required for the transmission and reception of data by a method wherein switches and first and/or second signal paths are provided in the device wiring region. CONSTITUTION:Along the periphery of a chip 1, a plurality of terminals 12, to apply switching signals to each of first signal paths 8, and a plurality of terminals 13, to output signals present on each of second signal paths 9, are provided. Switching signals are supplied in sequence to each of the terminals 12, and switches 7 which cells 2 are respectively provided with are activated in sequence. When the cells 2 are set to be active, signals are outputted at the terminals 13 coming from specified terminals 10 through the switches 7 and second signal paths 9. The output signals are used to check, for each of the cell 2, if wirings, to be built over the cells 2 and wiring region in a later process for driving cells 2, work properly.

Description

DETAILED DESCRIPTION OF THE INVENTION fb) Industrial Application Field The present invention relates to a master slice type semiconductor integrated circuit device having a gate array.

(B) Conventional technology In general, in a master slice type semiconductor integrated circuit having a gate array, one or two layers of materials such as aluminum are used within a predetermined wiring area to configure a predetermined circuit. Perform the above wiring. Therefore, no other circuits were constructed within the wiring area.

On the other hand, as a method to facilitate the testing of large-scale logic circuits, there is a scan canvas method in which a means such as a shift register is provided in the circuit to set test data or observe operation results (for example, Publication No. 56-4942).

In order to apply this scan canvas method, a shift register equipped with a means for inputting or outputting data in parallel is wired in the wiring area in advance in JP-A-59-4.
No. 6045 discloses n.

This makes it possible to scan in or scan out test data (setting or reading data through the entire scan canvas made up of shift registers) by subsequently performing predetermined wiring. be. However, in the scan path method, one shift register is required for each cell that inputs or outputs data, so a relatively large area of the wiring area is occupied by elements other than the original wiring. father,
There are drawbacks such as the time required to transmit and receive data is proportional to the number of stages of the shift register, and the time required to transmit and receive one piece of data is long.

Problems to be Solved by the Invention The present invention takes into account the above-mentioned drawbacks by reducing the space occupied by the necessary circuit for cell checking in the wiring area V and shortening the time for data transmission and reception. The purpose is to

(b) Means for Solving the Problems The present invention provides an area consisting of a uniform number of cells for forming a gate, a wiring area for forming a desired circuit by wiring between the cells, and a total area for forming a desired circuit. In a master slice type semiconductor integrated circuit device formed by arranging, in the wiring region,
a switch connected to a specific terminal of the cell and driven to monitor the state of the specific terminal; and a first signal path for applying a switching signal to the switch to drive the switch; and a second signal path for outputting a status signal.

(E) Function The present invention includes a switch for checking the cell in the wiring area, a first signal path for applying a switching signal to the switch to drive the switch, and/or a state signal of a specific terminal of the cell through the switch. Since the semiconductor integrated circuit device is provided with a second signal path for outputting, wiring for interconnection of a plurality of cells is formed in the wiring area of this semiconductor integrated circuit device in order to configure a predetermined circuit, and then By using all 2 signal paths and setting the above switch to the active state,
You can check the status of a specific terminal of a cell.

In the present invention, for this check, it is only necessary to provide a switch and a first and/or second signal path for operating the switch and outputting a signal through the switch, in the wiring area. The area occupied by the check circuit within the wiring area can be reduced, and the time required for transmitting and receiving check data can be shortened.

(f) Embodiment FIG. 1 is a plan view showing the conceptual structure of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a partially enlarged view of the same device.

In FIG. 1, (1) shows one chip that constitutes a gate array, and on this chip there are a plurality of (six in the illustrated example) cell rows (2a), (2b), (2c). and wiring areas (3a) (3b) installed between each cell column.
It is equipped with Each cell row has a large number of cells in the horizontal direction (3#), and each cell is configured as shown in FIG. 2, for example.

This cell includes the first and second transistors (4a) (4b) constituting the 10th MO8 and the fifth and fourth transistors (5a) (5b) constituting the iZcMO8, which are indicated by white circles. The ratio terminal (6) is not connected at the master stage, but is connected in a later process according to the requirements of circuit design. Although the internal configuration of the cell is not limited to that of the embodiment and can be modified in various ways, the details thereof will not be particularly useful for understanding the present invention, and therefore will not be described in detail.

The wiring areas (3a) and (3b) include switches (7) and 81
) A first rt4 comprising a first signal path (8) and/or a second signal path (9), and a second layer in which a predetermined wiring is formed on the first layer via an interlayer insulating film. It is equipped with

In this embodiment, the first signal path (8) for applying a switching signal to the gate terminal of the switch (7) is connected to the cell column (2a).
A plurality of second signal paths (9) are arranged in the direction crossing the cell rows (2a), etc., and a plurality of second signal paths (9) are arranged in the direction crossing the cell rows (2a), etc., and output signals from the specific terminals (101) of the cells (2) through the switches (7). The first signal path (8) of III is formed on the second layer near the intersection of both signal paths. , or the second signal path (all or the vicinity of the intersection 91 may be formed on the second layer). It is also possible to conduct multi-layer wiring under the second layer without using the first and second signal paths, so that the first and second signal paths are mutually insulated, and both signal paths are connected to each other.

The switch (71) is configured in the wiring area (3a) at the master level, and the source electrode of this switch (71) is connected to the specific terminal u1 of the cell (2), and the drain electrode is connected to the second signal path. (9), and its gate electrode is further connected to the first signal path (8).

At the periphery of the chip fi+, there are a plurality of terminals a3 for applying switching signals to each of the first signal paths (8), and a plurality of terminals (13) for outputting signals on each of the second signal paths (9).
1. By sequentially applying a switching signal to each of the plurality of terminals (121) and sequentially activating the switches installed in each cell, when the cell (2) is set to the active state, the plurality of terminals (131 includes a switch (7) and a second signal path (9) from the specific terminal C1α.
), an output signal is obtained through which it is possible to check, for each cell, the quality of the wiring formed in the subsequent process to drive the cell and the wiring area. Note that to set cell (2) to the active state, a predetermined logic circuit is completed by further wiring the master one-stage device using the wiring area, and then predetermined data and clocks are added to this logic circuit. This is achieved by giving

(G1. Effects of the Invention The present invention disposes switches and first and/or second signal paths in the wiring area of the device to enable cell checking using the scan canvas method, making it possible to effectively utilize the wiring area. In addition, the circuit for this check is extremely simple and occupies a small area in the wiring area.

Furthermore, the state of the cell can be directly observed, and the time for data transmission and reception can be shortened compared to the conventional example using a shift register.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the conceptual structure of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a partially enlarged view of the device.

Claims (1)

[Claims] (1) In a master slice type semiconductor integrated circuit device in which a region consisting of a plurality of cells for forming a gate and a wiring region for forming a desired circuit by wiring between the cells are arranged. , a switch connected to a specific terminal of the cell and driven to monitor the state of the specific terminal; a first signal path for applying a switching signal to the switch to drive the switch; or a second signal path for outputting a state signal of the specific terminal through the switch.