JPH03127846A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To arrange connection terminals on a chip at a pitch, narrower by a factor of an integer than a conventional one, by installing testing terminals for a plurality of connection terminals, many of which are arranged on a semiconductor chip at arrangement pitches suitable for bringing the needles of a testing probe into contact with the testing terminals. CONSTITUTION:The tips of needles 53 of a testing probe 50 are brought into contact with an input terminal 14 of a chip 10 and a testing terminal 20, thereby connecting the chip 10 with a testing equipment. During the test for each chip 10 in a wafer 1, logic states '0', '1' of a switching command are changed over, and an output circuit 13 and a latching circuit 12 connected with two output terminals to be tested via the testing terminals 20 are changed over. Thereby the arrangement pitch of connection terminals 15 on an integrated circuit device chip wherein test is enabled by using the testing prove 50 in which the needles 53 are arranged at the same tip pitches as the conventional ones can be reduced by a factor of an integer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device having a large number of external connection terminals and suitable for driving, for example, a printing element of a printer device or a pixel of a display panel device.

[Conventional technology]

With the advancement of integrated circuit technology, it has become possible to incorporate high-voltage or large-current transistors suitable for directly driving loads as described above into integrated circuits, and further advances in high-integration technology have increased the number of load driving circuits that can be incorporated. It has been increasing.

For example, while a normal display panel requires 640 display data lines and the same number of drive circuits, at first the number of built-in circuits in one chip was 16, which required 40 chips, but recently the number of circuits has increased. increases to 64 and requires only 10 chips. Fifth
The display panel driving chip shown in the figure is shown.

In the chip 10 of FIG. 5, there is a shift register 11. Latch circuit 12. It incorporates an output circuit 13, etc., loads a series of display input data Di from the lower input terminal 14 into the shift register 11 by a shift pulse SP, and responds to the output of each stage in synchronization with the latch command LS. The data is temporarily stored in the latch circuit 12, and an output voltage corresponding to the stored content is outputted all at once from the output circuit 13 to the load via the output terminal 15 in synchronization with the control signal CS.

Although the number of output terminals 15 in FIG. 5 is 10 for convenience of illustration, in reality, as mentioned above, they are provided unevenly in the dozens, and the same number of latch circuits 12 and output circuits 13 are also incorporated. It will be done.

By the way, as is well known, the chip 1 of such an integrated circuit device
It is necessary to first complete the test with a large number of chips 10 fabricated on one wafer, and remove defective chips after separating them from the wafer. During the test in this wafer state, each chip 10 is connected to its connection terminal input terminal 14 and output terminal 1 as
It is necessary to apply the needle of the test probe to 5 and connect it to the test equipment in sequence. It is well known that
Next, this procedure will be explained with reference to FIG.

In the top view of FIG. 4(a), the main body of the test probe 50 is a so-called printed wiring board, and its insulating substrate 51
A large number of wiring conductors 52 are arranged radially on the top, and the base of the above-mentioned needle 53 is fixed and connected to the inner end thereof, as shown in the enlarged cross section of the main part in Figure 0), and the outer end thereof is fixed and connected. For example, a connecting pin 54 as shown in the figure is used for connection with the test equipment.
is provided.

The needles 53 are usually made of a hard, highly elastic metal material such as tungsten, and their sharp tips are arranged at the same pitch as the connection terminals on the chip 10, as shown in FIG. A window 55 is provided in the insulating substrate 51 so that the contact state of the tip of the needle 53 with the connection terminal of the tip 10 can be confirmed.
is dawning.

During testing, the tip of the needle 53 is connected to the input terminal 1 of the chip 10 to be tested within the wafer 1, as shown in FIG.
After positioning the test probe 5o on wafer 1,
By pressing the needle 53 with a predetermined pressure to slightly bend the needle 53, the necessary contact pressure is applied between the tip and the connecting terminal. Note that although connection pads are used as connection terminals such as the input terminal 14 in this figure, bump electrodes protruding from the chip surface may also be used.

[Problem to be solved by the invention]

However, as the number of built-in circuits in a chip increases and the number of connection terminals such as output terminals increases, it becomes extremely difficult or impossible to manufacture a test probe equipped with the above-mentioned needle.

This is because if the number of needles on the test probe side is increased in accordance with the increase in the number of connection terminals on the chip side, the bases of the needles compete with each other, making it difficult to arrange them properly. That is, if the needle is bent as described above to have the mechanical strength necessary to apply sufficient contact pressure between the tip and the connecting terminal, the base of the needle will be 200 to 30
When the diameter becomes about 0 n and the number increases, the bases compete with each other due to their arrangement. For this reason, even though the tip of the needle can be narrowed down to a diameter of about 20 to 30 μm, the minimum practical limit for the arrangement pitch of the tips is 80 to 100 μm, and if the number of connection terminals on the tip is about 100 or more, the number of terminals will be the same. It becomes impossible to arrange the needles on the test probe. In addition, on the chip side, the connection terminal is 20 to 30 μm.
3 square or diameter microbump electrodes or small connection pads
It is easy to fabricate with an arrangement pitch of 0 to 50μ.

As described above, in integrated circuit devices having a large number of connection terminals, there is a problem in that test probes become a bottleneck and the long-awaited high integration technology cannot be fully utilized.

SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and to enable testing of integrated circuit devices using a test probe equipped with a needle even if the number of connection terminals is increased and the arrangement pitch thereof is narrowed.

[Means to solve the problem]

According to the present invention, this purpose is achieved by providing test terminals with a larger arrangement pitch than between the connection terminals for each of the plurality of connection terminals that are incorporated into the chip of the integrated circuit device at a narrow arrangement pitch, and A switch circuit that can connect and separate the two is inserted between the connection terminal and a switch control circuit that controls this switch circuit so that the connection terminal is selectively connected to the test terminal in sequence. This method is distantly related by specifying a connection terminal to be connected to a test terminal using a circuit, and allowing the test to be performed while switching the integrated circuit portion within the chip to be tested via the test terminal.

Note that it is advantageous to arrange the test terminal near the scribe line that isolates the chip from the wafer in order to effectively utilize the chip area.

Further, although this test terminal can be a bump electrode, it is usually easiest to use a connection pad and is advantageous for chip mounting.

The switch circuit can most easily be constructed with a single transistor, but it is advantageous to use a so-called analog switch circuit in that it does not allow current to flow in both directions and can only apply voltage.

[Effect]

The present invention focuses on the fact that when an integrated circuit device has a large number of connection terminals, it is possible to separate and test the integrated circuit in a chip into circuit parts that are directly connected to each of most of the connection terminals except for a few connection terminals. A test terminal is provided in common for each of the plurality of connection terminals that can be tested separately, and the test terminals are arranged at a pitch that is multiple times the arrangement pitch of the connection terminals. By adjusting the pitch of the connecting terminals on the integrated circuit device chip, which can be tested using a test probe whose needles are arranged at the same tip pitch as before, the arrangement pitch of the connecting terminals on the integrated circuit device chip can be reduced to 1, which is smaller than the conventional multiple pitch. be.

That is, as a specific means for switching the integrated circuit portion within the chip to be tested via the test terminal, the present invention provides a switch circuit as described in the above structure between the test terminal and each connection terminal. In addition, a switch control circuit is provided to control the switch circuit so as to selectively and sequentially connect a plurality of connection terminals to the test terminal.

〔Example〕

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of an integrated circuit device according to the present invention, FIG. 1(a) is a top view of the chip, and FIG. Since parts corresponding to those in FIG. 5 are given the same reference numerals, a description of the overlapping parts will be omitted.

In FIG. 1(a), a large number of chips 10 arranged in rows and columns within a wafer 1 are approximately the same size as in the case of FIG. Although the number of input terminals 14 is the same as before, for example, latch circuits 12 and output circuits 13 on the blind side and the same number of output terminals 15 are incorporated.

The input terminals 14 and output terminals 15 as connection terminals of the chip 10 are, for example, connection pads, and for example, the former has a size of 70μ square and an arrangement pitch of 100μ, while the latter has a half size of 35μ square and 50 fm. It is incorporated with the array pitch. In this example, the test terminal 20 according to the present invention is 2
They are provided individually, and their size and arrangement pitch are the same as those of the input terminals 14. Of course, if the chip 10 is to be further integrated, a test terminal 20 can be provided for every three output terminals 15, and the output terminals 15 can be arranged at a pitch of 30μ, for example, with a size of 20u square.

The switch circuits 30 in the present invention are arranged in parallel for each output terminal 15, and the open/close states are controlled by a common switch control circuit 40 shown at the top of the figure. In addition, as in this example, the test terminal 20 and the switch circuit 30
By arranging them in the scribe zone between the scribe line SL for isolating the chip 10 from the wafer 1 and the output terminal 15, the so-called idle area can be effectively utilized.

The switch circuit 30 includes, for example, a p-channel field effect transistor 31, as shown in the enlarged circuit diagram of the main part in FIG. 1(b).
and an n-channel field effect transistor 32. In this example, one end of each of the two switch circuits 30 is connected to the two output terminals 15a and 15b, and the other end is a test terminal. 20.

The switch control circuit 40 controls the gates of the field effect transistors for the switch circuit 30 via four control lines CL in this example, and receives the switch command S and the power supply voltages Vd, Vs from the input terminal 14, and controls the gates of the field effect transistors for the switch circuit 30 through four control lines CL. The command S and its complementary signal from the inverter 41 are applied to the gate control voltage generation circuit 42, and the two gate control voltages for the p- and n-channel field effect transistors 31, 32 and their complementary signals from the inverter 41 are applied to the control line. Put it on CL. As can be easily seen, by switching the logic state of 0.1 of the switch command S, the output terminal 15a is alternately closed or opened every other switch circuit 30.
and 15b can be connected to the test terminal 20 alternately.

Chip 10 in this embodiment configured as above
The test procedure is the same as in the previous figure 4, and as shown in the figure (b), the tip of the needle 53 of the test probe 50 is connected to the tip 10.
The chip 1 is brought into contact with the input terminal 14 of the chip 1 and the test terminal 20.
Connect 0 to the test equipment. During the test on each chip 10 in the wafer 1, by switching the logic state of 0.1 of the switch command S as described above, the two output terminals 15 to be tested are connected via the test terminal 20. The output circuit 13 and latch circuit 12 are switched.

FIG. 2 shows a different embodiment of the invention. The integrated circuits in the chip 10 in this example are arranged symmetrically, and the latch circuit 12 and the output circuit 13 are arranged on both sides of the shift register 11 as shown in the figure.
arranged in rows. The switch circuits 30 are arranged on the outside, and test terminals 20 arranged along two opposing sides of the square chip are provided for every two output terminals 15 in this example as well. A pair of switch control circuits 40 are provided, and the input terminals 14 are arranged on the upper and lower sides of the chip.

In this embodiment, the number of built-in circuits is considerably larger than that of the embodiment shown in FIG.
0, but the test is input terminal 14 and test terminal 20
There is no difference from the previous example in that it is carried out through .

FIG. 3 shows some examples of switch control circuits. The figure (a) shows a case where there are two control lines CL, and the switch control circuit 40 is composed of a single inverter 41, and the switch command S and its complementary signals are placed on the two control lines CL. Output terminal 15 corresponds to the O or 1 logic state of S.
a or 15b are alternately connected to the test terminals 20.

In the example shown in FIG. 3B, in order to be able to disconnect both the output terminals 15a and 15b from the test terminal 20, the switch command S is 2-bit data consisting of So and Sl. The switch control circuit 40 is composed of an inverter 41 that generates a complementary signal for each bit, and two Nant gates 42 and a NOR gate 43 that receive the bit signal and the complementary signal as shown in the figure, and the outputs of these logic gates are four. control line CL
be carried on.

In this example, a value between 0 and 3 can be specified for the switch command S, and in the case of 0 and 3, both output terminals 15a and 15b are disconnected from the test terminal 20, and in the case of 1, the output terminal 15a is disconnected from the test terminal 20. , 2, the test terminals 15b are connected to the test terminals 20, respectively.

As can be seen from the embodiments described above, the present invention is not limited to these embodiments, and can be implemented in various forms.

〔Effect of the invention〕

As described above, in the present invention, by providing test terminals for each of the plurality of connection terminals arranged on a semiconductor chip at a pitch suitable for contacting the needles of the test probes, the connection terminals on the chip are 1/2 of conventional
By inserting a switch circuit between the test terminal and each connection terminal, controlling this with a switch control circuit, and sequentially connecting the connection terminals to the test terminal, the test It is possible to proceed with the test via the test terminal while switching the integrated circuit portion within the chip to be tested.

As a result, even if the number of connection terminals built into an integrated circuit device chip is increased multiple times compared to the conventional method, the chip can be tested in exactly the same way as before using a test probe equipped with needles with the same tip arrangement pitch as before. Since testing is possible, the present invention removes the conventional testing restrictions on the high integration of integrated circuit devices with a large number of connection terminals, and promotes the rationalization of integrated circuit devices due to high integration.

In addition, in the implementation of the present invention, there is no need to increase the manufacturing process of the integrated circuit device compared to the conventional one, and the chip size can be reduced substantially from the conventional one by rationally arranging the test terminals and switch circuits as exemplified in the embodiment. It is possible to keep it to the same level as above.

This effect of the present invention is particularly useful for integrated circuit devices that drive a large number of loads such as printing elements of printers and pixels of display panels. By mass producing and providing economical integrated circuit device chips, we can contribute to the further rationalization and development of this type of device.

[Brief explanation of the drawing]

1 to 4 relate to the present invention; FIG. 1 is a top view of a chip and a circuit diagram of essential parts of an embodiment of an integrated circuit device according to the present invention, and FIG. 2 is a diagram of a different embodiment of an integrated circuit device according to the present invention. A top view of an integrated circuit device chip, FIG. 3 is a circuit diagram showing some aspects of the switch control circuit, and FIG. be. FIG. 5 is a top view of a chip for an integrated circuit device according to the prior art. In these figures, 1: wafer, 10: integrated circuit device chip, 11: shift register, 12: latch circuit, 13: output circuit, 14:
Input terminals as connection terminals, 15.15a, 15b
: Output terminal as a connection terminal, 20: Test terminal or connection pad, 30: Switch circuit, 31: P channel field effect transistor, 32: N channel field effect transistor, 40: Switch control circuit, 41: Inverter, 42: Gate control voltage generation circuit, 43: NAND gate, 44: NOR gate, 50: Test probe, 51: Insulating substrate, 52: Wiring conductor, 53 Nib lobe needle, 5
4: Connection pin, 55: Window, Di: Display data manually, Do
: Display data output, CL: Control line for switch circuit, C3: Control signal, LS: Latch command, S: Switch command, so, sl: Switch command data bit, SL scribe line, SP: Shift pulse, Vd, Vs :
The power supply voltage is

Claims (1)

[Claims] An integrated circuit device in which a large number of external connection terminals are arranged on a semiconductor chip, and test terminals that are commonly provided for multiple connection terminals and arranged at a larger pitch than between the connection terminals. , a switch circuit inserted between each connection terminal and the test terminal so that both terminals can be connected and separated, and a switch control circuit that controls the switch circuit to selectively connect the connection terminals to the test terminal in sequence. An integrated circuit device having a switch control circuit that specifies a connection terminal to be connected to a test terminal to switch the integrated circuit portion of the chip to be tested via the test terminal.