KR200285963Y1 - Probe card by Parallel Probing Method - Google Patents

Abstract

The present invention relates to a probe card for testing semiconductor devices, and to provide a probe card for 32 parallel tests using a probe card for 16 parallel tests, and to perform 32 parallel tests using the existing 16 parallel test tester as it is. A printed circuit board comprising a drive terminal for inputting a drive signal to a device on a wafer, and external connection terminals including input and output terminals for inputting and outputting test signals, respectively, as a card for semiconductor device probes. Probe pins, each connected to a terminal, comprising: and at least one or more of the driving terminals provides a probe card for a semiconductor device test, characterized in that connected.

Description

Probe card by Parallel Probing Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and more particularly, to a probe card for testing a semiconductor device used for inspecting electrical characteristics of a semiconductor device formed on a wafer.

A semiconductor device is completed through a number of processes in order to achieve its performance in one complete semiconductor package. The processes can be broadly divided into wafer production, fabrication (FAB), and assembly processes.

In particular, a plurality of semiconductor devices are formed on a wafer by a FAB process, and the plurality of semiconductor devices are screened for good or bad through electrical die sorting (EDS). The purpose of the electrical characteristic test is to 1) select the quantity and defects of each semiconductor element on the wafer as described above, 2) repair the repairable semiconductor element among the defective semiconductor elements, and 3) FAB. This is to feed back the problem in the process early, and 4) to reduce the cost of assembly and inspection by early removal of the defective semiconductor device.

The equipment used in the electrical property inspection process is composed of a tester and a probe system, and a probe card is installed in the probe facility to be in mechanical contact with electrode pads of semiconductor elements on the wafer. It is. The probe card is a very thin probe pin that is fixed to the printed circuit board. The signal generated by the tester is transmitted to each probe pin installed on the probe card through the probe equipment, and the signal transmitted to the probe pin is The pins are transferred to the electrode pads of the semiconductor device on the wafer in contact with each other to check whether the semiconductor device is good or defective.

Probe cards are divided into probe cards that can be tested in parallel with single, dual, four, eight and eight hexa semiconductor devices, depending on the measurement method. Can be.

A circuit diagram 40 of a conventional 16 parallel test probe card is shown in FIG. In FIG. 1, the two rows and eight rows are arranged to represent semiconductor elements 32 on a wafer, and "Drv" and "I / O" are external connection terminals 12 implemented on a printed circuit board, and "Drv". Indicates a drive terminal 11, and " I / O " indicates an input / output terminal 13 ". The line connecting the external connection terminal 12 and the semiconductor elements 32 corresponds to the probe pin 20. Elements 32 in rows 1 and 2 are indicated by numerals of " 1 " to " 16 " in turn. The driving terminal 11 and the input / output terminal 13 connected to the elements 32 are divided into alphabets, and the numerals and the alphabetical order displayed on the elements 32 correspond to each other. For example, it is represented by "DrvA _1-n " which shows the drive terminal of the element shown by 1. As shown in FIG. At this time, the letter A corresponds to the element 1, and 1 to n indicate the number of drive terminals. The input / output terminals of element 1 are represented by "I / OA ₁ to _{n &} quot ;, the letter A corresponds to element 1, and 1 to n indicate the number of input / output terminals.

Referring to FIG. 1, a driving terminal 11 and an input / output terminal 13 are formed to input driving signals to 16 elements 32 on a wafer so that 16 parallel tests can be performed, and input / output of test signals. have.

That is, as shown in FIGS. 2 to 4, the circuit wiring including the input / output terminal 13 and the driving terminal 11 is connected to the printed circuit board 10 to input and output the test signal to each element 32 individually. The probe pins 20 are joined to the input / output terminal 13 and the drive terminal 11 formed on the upper surface of the printed circuit board 10, respectively. Probe pin 20 is a needle type (needle type) has a structure in which the needle 24 is formed on the pin protector 22 of epoxy material, the probe is made by the needle (24).

In the center portion of the printed circuit board 10, a probe region 15 for probes of the elements 32 in two rows and eight rows, and external connection terminals 12 formed on both sides of the probe region 15 are provided. Include. In FIG. 2, for convenience of description, four rows and eight columns of elements to be tested are displayed in the probe region 15 of the printed circuit board, and illustration of the probe pin is omitted. The first external connection terminals 12a formed on the outside of one row are connected to the devices in one row, and the second external connection terminals 12b formed on the outside of the second row are connected to the devices in two rows. The probe pin 20 connected to the external connection terminals 12 extends toward the probe region 15. The outside of the printed circuit board 10 is an area in which pogo pin pads 14 which are electrically connected by pogo pins 34 of the test head are formed, and other elements and circuits are formed in other areas. Wirings are formed. Of course, the probe card 50 is connected to the test head opposite to the surface on which the probe pin 20 is formed. The power block 17 and the ground block 19, which are sequentially formed between the external connection terminals 12 and the probe region 15, are connected to the elements 32 by a probe pin 20.

The number of input / output terminals 13 provided per element 32 is eight, but four input / output terminals 13a are actually used. Some printed circuit boards support 16 input / output terminals. Reference numeral 13b denotes an extra input / output terminal.

On the other hand, in the case of implementing the 32 parallel test probe card in the same manner as the conventional 16 parallel test probe card 50, in order to connect the input / output terminal and the driving terminal to 32 elements individually, the number of driving terminals is doubled. Therefore, the number of probe pins formed on the printed circuit board also increases by the number of drive terminals. In addition, a tester having 32 parallel channels must be provided separately.

In more detail, the 16 parallel test probe card 50 also has an extra input / output terminal 13b except for the input / output terminal 13a to which the probe pin 20 is connected. The 16 parallel test probe card 50 can also be used as a 32 parallel test probe card. However, since the drive terminal 11 formed on the 16 parallel test probe card 50 cannot provide the drive terminal necessary for the 32 parallel test, the drive terminal 11 corresponding to the drive terminal 11 of the 16 parallel test probe card corresponds to twice the number. 32 parallel test probe cards with drive terminals shall be provided.

Therefore, as the number of probe pins increases, the area occupied by the probe pins, that is, the area occupied by the input / output terminals and the driving terminals, increases, and a tester having 32 parallel channels is required in addition to the new 32 parallel test probe card.

Therefore, an object of the present invention is to enable the 32 parallel test using the existing 16 parallel tester as it is.

Another object of the present invention is to provide a probe card for 32 parallel tests using a probe card for 16 parallel tests.

1 is a circuit diagram for a probe card for 16 parallel test according to the prior art,

2 is a plan view schematically showing the probe card according to FIG. 1;

3 is a plan view illustrating an input / output terminal and a driving terminal formed on a printed circuit board of a probe card;

4 is a cross-sectional view illustrating a probe pin connected to a driving terminal of a printed circuit board;

5 is a circuit diagram for a 32 parallel test probe card according to the present invention;

6 is a plan view schematically showing a probe card according to FIG. 5;

7 is a plan view illustrating an input / output terminal and a driving terminal formed on a printed circuit board of a probe card;

8 is a cross-sectional view illustrating a state in which two probe pins are connected to a driving terminal of a printed circuit board.

9 is a circuit diagram including a resistor formed between a drive terminal and a parallel structure needle;

<Description of the code | symbol about the principal part of drawing>

10, 60: printed circuit board 11, 61: drive terminal

12, 62: External connection terminal 13, 63: I / O terminal

14, 64: pogo pin pad 15, 65: probe area

20, 70: probe pin 22, 72: pin protector

32, 82: element 50, 100: probe card

35: resistance

In order to achieve the above object, a probe card for testing a semiconductor device, comprising: a printed circuit board having a drive terminal for inputting a drive signal to a device on a wafer and external connection terminals including input and output terminals for inputting and outputting test signals, respectively; And a probe pin connected to the input / output terminal and the driving terminal, respectively.

Provided is a probe card for testing a semiconductor device, wherein two probe pins are connected to at least one of the driving terminals.

It is possible to connect two probe pins to all drive terminals according to the invention.

The external connection terminals according to the present invention are disposed on both sides of an area where four rows and eight rows of sources on the wafer to be probed are located, but are disposed outside one row and four rows. Probe rows and rows of devices, and external connections near four rows probe devices in rows three and four.

In addition, two probe pins are provided at the driving terminal close to one row so as to probe the same electrode pads of the semi-elements positioned in the same column of the first row and the second row to be connected to the driving terminals of the first external connection terminal. Two strands of probes at the drive terminals close to the four rows, so as to be able to probe the same electrode pads of the semi-elements located in the same columns of three rows and four rows to be drawn out and connected to the drive terminals of the second external connection terminals The pin is withdrawn. The probe pin is a needle type.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

Fig. 5 is a circuit diagram 90 for a probe card for 32 parallel test according to the present invention. In FIG. 5, the four-row and eight-row arrangement represents the elements 82 of the wafer, and "Drv" and "I / O" are external connection terminals 62 implemented on a printed circuit board, and "Drv". Denotes the drive terminal 61, and " I / O " The line connecting the external connection terminal 62 and the elements 82 corresponds to the probe pin 74. The elements 82a in the 1st and 4th rows are represented by numbers of "1" to "16" in order, and the elements 82b of the 2nd and 3rd rows shared by the elements 82a of the 1st and 4th rows are in turn. Numerals " 1 '" and &quot;16'" The division of the driving terminals shared by the elements is alphabetical, and the division of the input / output terminals respectively connected to the elements is indicated by "alphabet" and "alphabet". The numbers and alphabetical order of the devices are displayed in correspondence with each other. For example, "DrvA ₁ to _n " are used to indicate shared drive terminals for devices marked 1 and 1 '. At this time, the letter A corresponds to the elements 1 and 1 ', and 1 to n indicate the number of drive terminals. The input / output terminals of the device of 1 'are represented by "I / OA' _1-n ", the letter A 'corresponds to the element 1', and 1-n indicates the number of input / output terminals. Hereinafter, the elements 82a in the 1st and 4th rows are referred to as reference elements, and the elements 82b in the 2nd and 3rd rows are referred to as shared elements.

Referring to FIG. 5, a driving terminal 61 and an input / output terminal 63 are formed to input driving signals to 32 elements 82 on a wafer so as to perform 32 parallel tests, and to input and output test signals. . At this time, by sharing the drive terminal 61, it is implemented to test in parallel the four rows, eight columns (32) of the elements 82 on the wafer as 16 parallel channels. As a method of sharing the drive terminal 61, it is preferable to adopt the method of sharing elements 82 belonging to the same column of 1 row, 2 rows, 3 rows, and 4 rows. The input / output terminals 63 are connected to the 32 elements 82, respectively. 63a indicates an input / output terminal respectively connected to the reference elements 82a, and 63b indicates an input / output terminal respectively connected to the shared elements 82b.

As such, by sharing the drive terminals 61 in one, two, three, and four rows, only 16 parallel channels are needed to test the 32 devices 82. Therefore, the existing 16 parallel tester can be used as it is.

A probe card 100 for a parallel test according to the circuit diagram 90 of FIG. 5 will be described with reference to FIGS. 6 to 8. FIG. 6 is a plan view schematically illustrating the probe card 100 of FIG. 5. 7 is a plan view illustrating an input / output terminal 63 and a driving terminal 61 formed on a printed circuit board 60 of a probe card. 8 is a cross-sectional view illustrating a state in which two probe pins 70 are formed at a driving terminal 61 of a printed circuit board.

5 to 8, the probe card 100 includes an external terminal including a driving terminal 61 for inputting a driving signal to an element 82 on the wafer, and an input / output terminal 63 for inputting and outputting test signals, respectively. A printed circuit board 60 having connection terminals 62 formed thereon, and probe pins 70 connected to the input / output terminal 63 and the driving terminal 61, respectively. In particular, two probe pins 70 are bonded to one driving terminal 61 to share 32 parallel tests.

In the printed circuit board 60, external connection terminals 62 are formed at both sides of the probing area 65 for probing the elements 82 in four rows and eight rows. In FIG. 6, for convenience of description, four rows and eight columns of elements to be tested are displayed in the probe area 65 of the printed circuit board, and illustration of the probe pin is omitted. The external connection terminals 62 are formed outside the first row and the fourth row, the first external connection terminals 62a formed outside the first row are connected to the elements 82 of the first row and the second row, The second external connection terminals 62b formed on the outer side of the fourth row are connected to the elements 82 of the third row and the fourth row. The probe pin 70 connected to the external connection terminals 62 extends toward the probe region 65. The outside of the printed circuit board 60 is an area where the pogo pin pads 64 which are electrically connected by the pogo pins 84 of the test head are formed, and other elements and circuit wirings are formed in other areas. have. Of course, the probe card 100 is connected to the test head opposite to the surface on which the probe pin 70 is formed. Then, the power supply blocks 67a and 67b and the ground blocks 69a and 69b are alternately formed between the external connection terminals 62 and the probe region 65, and closer to the external connection terminals 62. The power block 67a and the ground block 69a are connected to the reference element 82a by the probe pins 70, and the remaining power block 67b and the ground block 69b are also connected to the probe pins 70 by the shared element 82b. )

Probe pin 70 is a needle type (needle type) has a structure in which the needle 74 is formed on the pin protector 72 of the epoxy (epoxy) material. Tungsten is mainly used as a material of the needle 74, and the end of the needle 74 is soldered to the printed circuit board 60 by soldering.

Comparing the conventional 16 parallel test printed circuit board 10 shown in Figs. 2 and 3 with the printed circuit board 60 according to the embodiment of the present invention shown in Figs. Except for 15 and 65, the same external wiring terminals 12 and 62 have the same circuit wiring. That is, the conventional printed circuit board 10 and the printed circuit board 60 according to the present invention have the same input / output terminals 13 and 63 and the driving terminals 11 and 61.

By the way, while the 32 parallel test can be performed with the printed circuit board 60 according to the present invention, only 16 parallel tests can be performed with the conventional printed circuit board. As described above, the first reason that the same parallel connection terminal as the 16 parallel test printed circuit board can be implemented with the 32 parallel test printed circuit board 60 is the driving terminal 61 of the printed circuit board according to the present invention. Since two probe pins 70 are bonded to each other, it is not necessary to form a driving terminal corresponding to the increased element. That is, as shown in FIG. 8, two probe pins 70, ie, needles 74, pulled out from the driving terminal 61 are in contact with the same electrode pads of neighboring elements 82.

The second reason is that a large number of input / output terminals are typically assigned to the printed circuit board compared to the number of input / output terminals substantially connected to the element 82. For example, in the case of FIG. 3, eight input / output terminals 13 are assigned per element 32, but since only four input / output terminals 13a are actually used, the case of the present invention is shown in FIG. Likewise, when the extra input / output terminal 63b is used as an input / output terminal of a neighboring element, it is not necessary to form an additional input / output terminal.

On the other hand, the reason why the input and output terminals 63 are not shared is that the test results for the respective devices 82 can be known only when the input and output of the test signals for the respective devices 82 are made independently. In the embodiment of the present invention, an example of a printed circuit board 60 having eight input / output terminals 63 is disclosed, but there are also 16 parallel test printed circuit boards providing about 16 input / output terminals. Four or eight of the 16 input and output terminals are used.

As shown in FIG. 8, two probe pins 70, which are bonded to one driving terminal 61, that is, the needle 74, may be implemented to be in contact with the same electrode pads of two neighboring semiconductor elements 82. Therefore, the length can be shorter than the needles drawn from the respective driving terminals, thereby minimizing the reflection noise.

On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding, and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented. For example, although the embodiment of the present invention is implemented as a 32 parallel test probe substrate using 16 parallel test probe substrates, it may be implemented as a 16 parallel test probe substrate using 8 parallel test probe substrates. That is, the configuration of doubling the number of semiconductor devices that can be tested by connecting two probe pins to a driving terminal and the configuration of connecting two probe pins to at least one driving terminal are within the scope of the technical idea of the present invention. .

In addition, since two probe pins are probed in parallel at one driving terminal 11, which is a feature of the present invention, when one element 82 is short, Even if defective, both elements 82 are determined to be defective. In order to solve this problem, a resistance 35 is applied between each needle 74 and the driving terminal 11 to compensate for the problem caused by the defect. That is, in the circuit diagram 36 of the driving terminal 11 and the needle 74, a signal is transmitted to the driving terminal through the resistor 35a on the extension line of the needle 74a. Due to the design of the needle 74 connecting the resistor 35, even if one element 82a is defective, it does not affect the other element 82b.

According to the structure of the present invention, by sharing the drive terminals of 1 row, 2 rows, 3 rows and 4 rows, only 16 parallel channels are needed to test 32 devices in parallel. Therefore, the existing 16 parallel tester can be used as it is.

Since the 32 parallel test probe card according to the present invention has the same driving terminal and input / output terminals as the 16 parallel test probe card, the 32 parallel test probe card can be easily implemented.

Further, since the 32 semiconductor devices on the wafer can be tested at once with the 16 parallel tester, the wafer can be tested in half the test time using the 16 parallel test probe card. That is, the test time for the wafer can be shortened in half.

Claims (6)

As a probe card for testing semiconductor devices, A printed circuit board having a driving terminal for inputting a driving signal to an element on the wafer and external connection terminals including input and output terminals for inputting and outputting test signals, respectively; And a probe pin connected to the input / output terminal and the driving terminal, respectively. A probe card for testing a semiconductor device, characterized in that two probe pins are connected to at least one driving terminal. The method of claim 1, The probe card for testing a semiconductor device, wherein two probe pins are connected to all the driving terminals. The method of claim 2, The external connection terminals are disposed on both sides of an area where four rows and eight rows of sources on the wafer to be probed are located, and are disposed outside the rows 1 and 4, The externally connected terminals close to the first row probe the first and second rows of devices on the wafer, and the externally connected terminals close to the fourth row probe the three rows and four rows of devices on the wafer. A probe card for testing semiconductor elements, characterized by the above-mentioned. The method of claim 3, wherein Two stranded probe pins are drawn out from the drive terminal close to the first row so as to probe the same electrode pads of the semi-elements positioned in the same column of the first and second rows to be connected to the drive terminal, Two probe pins are pulled out from the driving terminal adjacent to the fourth row so that the same electrode pads of the semi-elements positioned in the same column of the third and fourth rows to be connected to the driving terminal can be probed. Probe card for semiconductor element test. The method of claim 4, wherein The resistance is applied between each needle and the driving terminal of the parallel needle to compensate for the problem that both devices connected in parallel due to a failure of one device are treated poorly, so that even if one device 82a is defective, Probe card for testing semiconductor devices with no effect. The probe card according to any one of claims 1 to 4, wherein the probe pin is a needle type.