JPS62154638A - Semiconductor circuit inspecting device - Google Patents
Semiconductor circuit inspecting deviceInfo
- Publication number
- JPS62154638A JPS62154638A JP60297403A JP29740385A JPS62154638A JP S62154638 A JPS62154638 A JP S62154638A JP 60297403 A JP60297403 A JP 60297403A JP 29740385 A JP29740385 A JP 29740385A JP S62154638 A JPS62154638 A JP S62154638A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- circuit cell
- cell
- semiconductor
- sequentially
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Semiconductor Integrated Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は半導体回路の検査装置に関するもので、特には
半導体回路が同一基板内にマドリスク状に配置された半
導体装置の良否を検査する装置に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a semiconductor circuit testing device, and more particularly to a device for testing the quality of a semiconductor device in which semiconductor circuits are arranged in a Madrisk pattern on the same substrate. .
〈発明の背景〉
半導体製造技術の進歩に伴って半導体素子が著しく微細
化し、半導体基板に高密度に集積化され、各種機器の駆
動や制御のために集積回路装置が用いられている。<Background of the Invention> With advances in semiconductor manufacturing technology, semiconductor elements have become significantly smaller and more densely integrated on semiconductor substrates, and integrated circuit devices are used to drive and control various devices.
同一半導体基板内に繰返しパターンに回路セルをマトリ
クス状に形成し、これら回路セルを用途に応じて同一基
板上で配線したり、或いは回路セルに接続する電極及び
配線を設けた配線基板を上記回路セルが形成された半導
体基板に重ね合せることによって、半導体基板内の回路
セルから出力を取り出して機器を制御する構造の半導体
集積回路装置が提案されている。Circuit cells may be formed in a matrix in a repeated pattern on the same semiconductor substrate, and these circuit cells may be wired on the same substrate depending on the application, or a wiring board provided with electrodes and wiring to connect to the circuit cells may be used as the circuit. 2. Description of the Related Art A semiconductor integrated circuit device has been proposed in which a semiconductor integrated circuit device is placed on a semiconductor substrate on which cells are formed, and output is taken out from circuit cells in the semiconductor substrate to control equipment.
この種の装置の上記回路セルは、通常夫々半導体基板内
で独立して設けられており、従って製造工程の最終段階
で行なう検査工程では、各回路セルだ設けられた出力信
号取り出しのだめのAlパッドにプローブカードの電極
針を接触させ、各回路セル毎に良否を判定する方法が採
られる。The above-mentioned circuit cells of this type of device are usually provided independently within the semiconductor substrate, so in the inspection process performed at the final stage of the manufacturing process, the Al pads provided in each circuit cell are used to take out the output signal. A method is adopted in which the electrode needle of the probe card is brought into contact with the circuit cell, and the pass/fail of each circuit cell is judged.
しかし近年のように微細加工の技術が進歩し、高密度化
されてくると回路セルが小寸法になると共に電極パッド
領域も小さくなり、また密に配置されるようになってく
る状況下では、テスト装置のプローブカードとして回路
セル数に対応する電極針を作り込むことができず、上述
のような回路セルがマドリスクに配置された半導体集積
回路ではウェハー状態でテストすることが極めて困難に
なる。However, as microfabrication technology has advanced in recent years and density has increased, circuit cells have become smaller in size, electrode pad areas have become smaller, and they have become more densely arranged. It is not possible to fabricate electrode needles corresponding to the number of circuit cells as a probe card of a test device, and it becomes extremely difficult to test a semiconductor integrated circuit in a wafer state in which the circuit cells are arranged in a matrix as described above.
〈発明の目的〉
本発明は、同一半導体基板上にマトリクス状に多数の回
路セルが配置されてなる半導体集積回路装置のウェハー
状態でのテストを可能にするもので、テストのための入
力信号を回路セル間で順次バケツリレーさせることによ
り、出力端に導出されたデータに基いてリレー途中に経
由してきた回路セルの良否を判定し得る半導体集積回路
検査装置を提供する。そのため本発明は、アレイ状の各
回路セル間に検査信号の通過を制御するためのスイッチ
ング素子を設け、このスイッチング素子をアレイをなす
回路セル群の一方の回路セルから′他方の回路セルに向
って順次導通させて検査信号を転送させることにより経
由した回路セルの良否を判定する。<Object of the Invention> The present invention enables testing in a wafer state of a semiconductor integrated circuit device in which a large number of circuit cells are arranged in a matrix on the same semiconductor substrate. To provide a semiconductor integrated circuit testing device capable of determining the quality of a circuit cell passing through the relay based on data derived from an output terminal by sequentially performing a bucket brigade between circuit cells. Therefore, the present invention provides a switching element for controlling the passage of a test signal between each circuit cell in an array, and switches the switching element from one circuit cell to the other circuit cell in a group of circuit cells forming the array. The quality of the circuit cells passed through is determined by sequentially making the cells conductive and transmitting test signals.
〈実施例〉
同一半導体基板内に回路セル]a+ Ib、lc・・
が少なくとも一列、多くの場合は行及び列をもつマトリ
クス状に配置されている。上記回路セルの各単位は、同
一の回路構成に設けられ、例えばデータをラッチし得る
クロス結合されたトランジスタ素子を含んで構成されて
いる。各回路セル+a+1b+1cm・・の夫々には、
各回路セルから出力信号を取り出して他の回路と電気的
接続するための電極パラ)2a+ 2b+ 2c・
・が設けられ、該電極バッド2a+ 2b+ 2c
・・に、別途に設けられた配線基板やマトリスス液晶基
板上の電極バンプ(図示せず)を接触させて、回路セル
を配線基板や液晶基板側と電気的接続する。<Example> Circuit cells in the same semiconductor substrate] a+ Ib, lc...
are arranged in a matrix with at least one column, often rows and columns. Each unit of the circuit cell is provided in the same circuit configuration and includes cross-coupled transistor elements capable of latching data, for example. For each circuit cell +a+1b+1cm...
Electrode parameters for extracting output signals from each circuit cell and electrically connecting them to other circuits) 2a+ 2b+ 2c・
* are provided, and the electrode pads 2a+ 2b+ 2c
The circuit cell is electrically connected to the wiring board or liquid crystal substrate side by contacting electrode bumps (not shown) on a separately provided wiring board or matrix liquid crystal substrate.
上記回路セル群の同一アレイに属する回路セル1a+
1b+ Icに対して、回路セルlaとIb。Circuit cell 1a+ belonging to the same array of the above circuit cell group
1b+Ic, circuit cells la and Ib.
1bと1c間を接続する導体5 b+ 5 c s入
力端子3と回路セル1a間を接続する導体5a+及び出
力端子4と回路セル10間を接続する導体5dに双方向
スイッチング素子であるMOSFET 6 a+6b+
6c+ 6dが介挿される。該MO5FET6a
〜6dの夫々のゲートにはシフトレジスタ7から、オン
・オフを制御するだめの制御信号が与えられている。該
シフトレジスタ7は、入力端8に与えられたシフトデー
タが端子9に与えられるシフトクロックに基いて順次シ
フトされることにより、スイッチング素子6a〜6dの
いずれかのMOS F ETを導通させる。MOSFET 6a+6b+, which is a bidirectional switching element, is connected to the conductor 5b+ connecting between 1b and 1c, the conductor 5a+ connecting between the input terminal 3 and the circuit cell 1a, and the conductor 5d connecting between the output terminal 4 and the circuit cell 10.
6c+6d is inserted. The MO5FET6a
A control signal for controlling on/off is given from the shift register 7 to each of the gates 6d to 6d. The shift register 7 sequentially shifts shift data applied to an input terminal 8 based on a shift clock applied to a terminal 9, thereby making any of the MOS FETs of the switching elements 6a to 6d conductive.
回路セルがマトリクス状に配置されてなる半導体集積回
路においては、上記スイッチング素子は同一アレイに属
する隣接回路セル開缶に設けられるが、シフトレジスタ
7は各アレイの対応するスイッチング素子のゲートに夫
々制御信号を入力すること知より共通して設けることが
できる。In a semiconductor integrated circuit in which circuit cells are arranged in a matrix, the switching elements are provided in adjacent circuit cells belonging to the same array, and the shift register 7 controls the gates of the corresponding switching elements in each array. It is possible to provide a common device for inputting signals.
上記構造の半導体回路において、入力端子3に検査のた
めの論理データが与えられと、該論理データは、スイッ
チング素子6a+6b・・がシフトレジスタ7からの信
号に対応して順次オフからオンに切換えられる動作に伴
って、第1番目の回路セルIaから順次同一アレイ内の
回路セルをパケツリレー状に転送される。即ち例えばス
イッチング素子6bをオンさせることにより、第1番目
の回路セルIaに書込まれた入力端子3の論理データを
第2番目の回路セル1bに書込むことができる。尚この
時点でシフトレジスタ7によりスイッチング素子6aは
オフされている。同様に順次スイッチング素子を導通さ
せることによって、入力端子3に書込んだデータは出力
端子4にまで転送される。出力端子4に導出されたデー
タを、半導体回路のテストシステムに予め設定された正
常論理値と比較することにより、半導体回路を構成する
回路セルの良否を自動的に判定することができる。In the semiconductor circuit having the above structure, when logic data for inspection is applied to the input terminal 3, the switching elements 6a+6b, etc. are sequentially switched from off to on in response to signals from the shift register 7. Along with the operation, the circuit cells in the same array are sequentially transferred from the first circuit cell Ia in a packet relay manner. That is, for example, by turning on the switching element 6b, the logic data of the input terminal 3 written to the first circuit cell Ia can be written to the second circuit cell 1b. Note that at this point, the switching element 6a is turned off by the shift register 7. Similarly, the data written to the input terminal 3 is transferred to the output terminal 4 by sequentially turning on the switching elements. By comparing the data derived to the output terminal 4 with a normal logic value preset in a semiconductor circuit test system, it is possible to automatically determine the quality of the circuit cells forming the semiconductor circuit.
即ち転送途中の回路セルに漏洩や断線等の不良があれば
、所定レベルの出力信号が導出されず、アレイに属する
いずれかの回路セルに不良の起きていることが検出され
る。That is, if there is a defect such as leakage or disconnection in a circuit cell during transfer, an output signal of a predetermined level is not derived, and it is detected that one of the circuit cells belonging to the array is defective.
〈発明の効果〉
以上本発明によれば、各回路セルに電極ビンを当てるこ
となく、従来と同様のプローブカードにてウェハ状態で
マトリクス状の回路セルを有する半導体回路の良否を判
定することができ、高密度・微細化された半導体装置に
対しても、簡単な構成を付加することによって良否を自
動的に判定することができウェハテストができないため
に完成後にテストを実施し、そのために低い歩留りを強
いられていた半導体集積回路に対して製造の能率を著し
く改善することができる。<Effects of the Invention> According to the present invention, it is possible to judge the quality of a semiconductor circuit having a matrix of circuit cells in a wafer state using a conventional probe card without applying an electrode bottle to each circuit cell. By adding a simple configuration, it is possible to automatically determine pass/fail even for high-density and miniaturized semiconductor devices. Since wafer testing is not possible, testing is performed after completion, which results in low It is possible to significantly improve the manufacturing efficiency of semiconductor integrated circuits, which have been subject to high yields.
図は本発明による一実施例を示す半導体装置の概念図で
ある。
Ia+ 1b+ Ic:回路セル 2a、2b+2
c:電極バッド 3:入力端子 4:出力端子5a〜5
dニスイツチング素子 6:シフトレジ代理人 弁理士
福 士 愛 彦(他2名)、1α lb
、、にζThe figure is a conceptual diagram of a semiconductor device showing one embodiment of the present invention. Ia+ 1b+ Ic: Circuit cell 2a, 2b+2
c: Electrode pad 3: Input terminal 4: Output terminal 5a-5
d Niswitching element 6: Shift register agent Patent attorney Aihiko Fukushi (and 2 others), 1α lb
,, toζ
Claims (1)
々から導出された電極パッドを備えてなる複数の回路セ
ルと、 隣接する上記回路セル間の線路に挿入された双方向スイ
ッチング素子と、 該スイッチング素子のオン・オフを制御する制御回路と
を備え、上記スイッチング素子を順次オンさせて一端の
回路セルから入力されたデータを他端の回路セルから導
出して検査することを特徴とする半導体回路検査装置。[Claims] 1) A plurality of circuit cells arranged in a matrix array on the same substrate and each having an electrode pad led out from each circuit cell, and both circuit cells inserted into a line between adjacent circuit cells. directional switching elements, and a control circuit that controls on/off of the switching elements, and the switching elements are sequentially turned on to derive data input from a circuit cell at one end from a circuit cell at the other end for inspection. A semiconductor circuit inspection device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60297403A JPS62154638A (en) | 1985-12-26 | 1985-12-26 | Semiconductor circuit inspecting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60297403A JPS62154638A (en) | 1985-12-26 | 1985-12-26 | Semiconductor circuit inspecting device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62154638A true JPS62154638A (en) | 1987-07-09 |
Family
ID=17846047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60297403A Pending JPS62154638A (en) | 1985-12-26 | 1985-12-26 | Semiconductor circuit inspecting device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62154638A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6119250A (en) * | 1996-05-07 | 2000-09-12 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
-
1985
- 1985-12-26 JP JP60297403A patent/JPS62154638A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6119250A (en) * | 1996-05-07 | 2000-09-12 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
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