JPH0572295A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To make testing and analysis easier and obtain a semiconductor integrated circuit with a circuit structure simplified for facilitating the testing and analysis. CONSTITUTION:This semiconductor circuit 1 is made up of a flip chip part 7 having a plurality of internal circuits 20 to 2n arranged are input/output terminals 11 to 1n arranged in the perimeter of the flip chip part 7. Input/output terminals 30 to 3n are arranged in the flip chip part 7 for information corresponding to the internal circuits 20 to 2n arranged in the flip chip part 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a method of testing a semiconductor circuit and a structure of the semiconductor integrated circuit in consideration of the test.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor circuit such as an LSI, the characteristics of the semiconductor circuit,
Alternatively, the test may be performed to test the performance or to judge whether the internal circuit is good or bad.In that case, it is different from the normal data signal or input signal and is used only when the test is executed. The test control signal is used. In that case, an input / output terminal for inputting the test signal is required. However, in recent years, semiconductor integrated circuits have become large-scale and highly integrated, and along with this, it has become impossible to take many terminals for inputting test signals. If it is attempted to obtain many terminals for inputting the signal, it becomes impossible to obtain a large number of data signal input / output terminals that are originally required. Therefore, in the past, in order to perform the test efficiently, the internal circuit unit is divided into blocks for each function,
It is also considered that the test terminal is moved to another place, the number of test signals is reduced, or a scan path circuit or the like is provided to facilitate test analysis. However, in these conventional circuits, the design becomes complicated, and the proportion of circuits that are part of the test facilitation other than the original function is increasing.

[0003]

SUMMARY OF THE INVENTION The present invention provides a semiconductor integrated circuit in which the drawbacks of the prior art described above are improved, testing and analysis are facilitated, and the circuit is simplified for facilitating testing. With the goal.

[0004]

In order to achieve the above object, the present invention provides a semiconductor circuit having the following technical constitution. That is, in a semiconductor circuit composed of a flip chip part in which a plurality of internal circuits are arranged and an input / output terminal group arranged around the flip chip part, the flip chip part is provided with the flip chip part. The semiconductor circuit is provided with an input / output terminal for controlling input / output of information with respect to at least a part of the internal circuits arranged in the chip portion.

[0005]

In the present invention, by adopting the above-mentioned technical structure, in particular, a large number of test control signal input terminals are arranged in the flip chip section, so that the number of test dedicated signals does not matter. It is possible to simplify the operation of the test itself, including methods such as the division method. Further, in the present invention, the output of the cell existing inside the circuit can be taken out as it is as shown in FIG. 1, so that the internal state of the circuit can be measured at the time of testing and analysis. Further, if the circuit configuration is such that the input from the flip chip is input to the internal cell, the state of the cell inside the circuit can be set without the need for a huge amount of test data.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of semiconductor circuits according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a specific example of a semiconductor circuit according to the present invention, in which a plurality of internal circuits 20 to 2n are arranged, and a flip chip portion 7 and peripheral portions of the flip chip portion 7. In the semiconductor circuit 1 including the input / output terminal groups 11 to 1n, corresponding to at least a part of the internal circuits 20 to 2n arranged in the flip chip part 7 in the flip chip part 7. The semiconductor circuit is provided with input / output terminals 30 to 3n for controlling the input / output of information to / from the internal circuit. In the semiconductor circuit according to the present invention, the input / output terminals 30 to 3n arranged in the flip chip section 7 are used as input terminal sections for a dedicated instruction signal for testing. Alternatively, it may be used as an input terminal of a normal data signal. In the present invention, the input / output terminals 30 to 3n arranged in the flip chip portion 7 are also included.
It is preferable that the internal circuits 20 to 2n are connected to each other through selection means 40 to 4n composed of appropriate switching means, and a specific configuration of the selection means is shown in FIG. A switching circuit composed of MOS transistors as shown can be used. By adopting such a configuration, in the semiconductor circuit of the present invention, the input / output terminals 30 to 3n and the internal circuits 20 to 2n are selectively turned on / off.
It becomes possible to control to turn off. Therefore, in the semiconductor circuit of the present invention, the selecting means 40
It is preferable that the control means 50 for selectively controlling at least one of 4n to 4n is arranged in the flip chip portion 7. That is, in the semiconductor circuit according to the present invention,
The input / output terminal portion of the internal cell that constitutes the semiconductor integrated circuit is
It is formed in the flip chip independently of the original circuit connection, and is configured so that necessary signals can be taken out from the circuit surface.
It is also possible to form a bump portion in n to perform a normal signal processing, or to connect a probe to the input / output terminals 30 to 3n to perform a predetermined test based on a predetermined control signal. May be. FIG. 2 is an explanatory view of the principle of the present invention. In the example of FIG. 2, the output signal VIN of the test signal or the normal data signal input to the cell 20 is simply transmitted to the internal circuit of the next stage in the conventional configuration. In the specific example according to the present invention, the data is output from the node 1N to the input / output end 30 of the flip chip region 7, and thereby the performance test of the internal circuit is executed. In the specific example of FIG. 2, the flip chip area 7
No special circuit is added when outputting to the input / output end 30 of the. On the other hand, FIG. 3 shows the internal circuit 20 shown in FIG.
A selection circuit 40 composed of a MOS transistor is arranged between the input / output terminal 30 and the input / output terminal 30, and the connection between the internal circuit 20 and the input / output terminal 30 is established by utilizing the on / off operation of the MOS transistor. This is an easy configuration for turning on / off the connection. Therefore, turning on the MOS transistor
A control means 50 for controlling the OFF operation is provided to control the output to the input / output end 30 of the flip chip area 7. In the present invention, by connecting a test probe to the arbitrary input / output end 30, the output of an arbitrary or predetermined internal circuit existing inside the circuit, such as a cell or a counter, can be taken out as it is. Therefore, the internal state of the circuit can be measured during testing and analysis. Further, the internal state of the predetermined internal circuit to be measured can be easily set to the predetermined state. For example, when the internal circuit is a counter, it is possible to set the value of the counter to an arbitrary count value by applying a predetermined signal to the input / output end 30 connected to the counter. . That is, if the circuit configuration is such that the input from the flip chip is input to the internal cell, the state of the cell inside the circuit can be set without the need for a huge amount of test data. Further, in the present invention, when a normal data signal is input, the output state of a predetermined internal circuit can be taken out at an arbitrary location and at an arbitrary timing, so that the computer can be used. A test similar to the simulation performed by using it can be performed on the mounting chip, and the analysis can be performed. Further, in one embodiment of the present invention shown in FIG. 1, the selection means 40 to 4n are simultaneously turned on / off by one control means 50, but the present invention is concerned. The configuration is not limited, and the selection units 40 to 4n may be configured to be controlled individually or in predetermined groups. Further, in the embodiment of the present invention, the internal circuits 20 to 2n and the input / output end portions 30 to 3 are used.
Although n is shown as an example in which it is arranged in a one-to-one relationship, the present invention is not limited to such a configuration, and each of the selecting means 40 to 4n has an optimum and efficient inspection, It may be configured so as to be controlled for each group of an appropriate predetermined size within a range in which the test and the Schriller Shine can be executed. In this embodiment, when the control signal is "H", the output of each internal cell is output to the area bump. On the other hand, the control signal is "L"
, The cell output does not appear on the flip chip.

[0007]

As described above, according to the present invention, the effect that the actual internal state of the chip can be known as when analyzing by simulation is shown, and the test coverage is high with a small amount of test data. It is possible to carry out a test, and it greatly contributes to the reduction of the analysis work of the failure point and the reduction of the test data amount. Also, since it is possible to directly input signals from the flip chip to the cells in the chip, it is possible to set the status of the internal counter with a simpler circuit configuration than using a scan path circuit, and a smaller area It is possible to design a circuit in consideration of the test, and also to effectively use the input / output pads arranged around the chip by reducing the number of test pads by using the flip chip. become.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is an explanatory view of the principle of the present invention,

FIG. 3 is a diagram illustrating an example of a selection unit used in the present invention.

[Explanation of symbols]

 1-semiconductor circuit 7-flip chip area 11 to 1n-data signal input / output terminal portion 20-2n-internal circuit 30-3n-input / output terminal portion 40-4n-selecting means 50-control means

Claims (4)

[Claims] 1. A semiconductor circuit comprising a flip-chip part in which a plurality of internal circuits are arranged and an input / output terminal group arranged in the periphery of the flip-chip part in the flip-chip part. A semiconductor circuit, wherein an input / output terminal for controlling input / output of information to / from the internal circuit is provided corresponding to at least a part of the internal circuit arranged in the flip chip portion. 2. The semiconductor circuit according to claim 1, wherein the input / output terminal arranged in the flip chip portion constitutes an input terminal portion for a test signal. 3. The semiconductor circuit according to claim 2, further comprising a selection circuit for selectively controlling connection between the input / output terminal arranged in the flip chip portion and the internal circuit. 4. The semiconductor circuit according to claim 3, wherein a control circuit for selectively controlling at least one of the selection circuits is arranged in the flip chip portion.