JP3077809B2 - Semiconductor integrated logic circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated logic circuit. More specifically, a semiconductor integrated logic circuit having a larger number of output terminals than the number of test terminals of a general test device, and an effective test can be executed by a test circuit having a smaller number of test terminals than the number of output terminals. The invention relates to a configuration of a simple semiconductor integrated logic circuit.

2. Description of the Related Art A semiconductor integrated logic circuit is subjected to many types of tests at each stage from a wafer stage to after a package. Particularly, in order to test an internal operation of an integrated circuit, an output terminal of the integrated circuit and a test are performed. It is necessary to connect to the test terminal of the device.

Therefore, the number of output terminals of the integrated circuit to be tested and the number of test terminals of the test device need to completely correspond. Further, in the test at the wafer stage, in order to connect the output terminal formed on the wafer to the test device, a needle-shaped test probe having a finely processed tip is used.
Again, it is necessary to prepare the same number of test probes as the number of terminals of the integrated circuit on the wafer.

Problems to be Solved by the Invention On the other hand, especially in a semiconductor integrated circuit of a logic circuit, the number of output terminals tends to increase year by year. However,
Test equipment is generally very expensive, and it is extremely uneconomical to prepare a new test equipment each time for a product with a new specification.

Also, when a test is performed at the wafer stage, the test probe itself is expensive, and setting many test probes to fine terminals significantly lowers work efficiency.

Therefore, the present invention solves the above-mentioned problems of the prior art,
In many cases, it is an object of the present invention to provide a novel semiconductor integrated logic circuit which can perform an effective test with a test apparatus already having a small number of test terminals.

In other words, according to the present invention, a single chip is arranged such that each of a plurality of logic signals is output from a corresponding output terminal via a corresponding output buffer. A semiconductor integrated logic circuit formed thereon, wherein a signal line of a first logic signal is connected to an input of a corresponding first output buffer, and an output of the first output buffer is connected to a corresponding first output buffer. The signal line of the second logic signal is connected to the first input of the selector circuit, and the second input of the selector circuit is connected to the output terminal and the input of the input buffer. The output of the selector circuit is connected to the output of the input buffer, the output of the selector circuit is connected to the input of a second output buffer corresponding to the signal line of the second logic signal, and the output of the second output buffer is Connected to the second output terminal By controlling the selector circuit, the first output signal and the second logic signal are output from the second output terminal.
And the first logic signal is output from the second output terminal via a first output buffer and a second output buffer. Thus, a semiconductor integrated logic circuit characterized in that both output buffers can be tested simultaneously.

The main features of the logic circuit according to the present invention include: an output terminal including a bidirectional buffer; and an output terminal including a selector circuit having an input connected to the output side of the bidirectional buffer. I have.

That is, in the conventional logic circuit, in order to effectively test the logic signal output to the output terminal, it is inevitable to use a test circuit having the same number of test terminals as the number of output terminals of the logic circuit. there were.

On the other hand, in the logic circuit according to the present invention, in addition to the logic signal corresponding to the output terminal, the logic signal output to the other output terminal is supplied to the selector circuit provided at the predetermined output terminal. Input via the input buffer. Therefore, by controlling the selector circuit as needed, a logic signal of another output terminal can be observed from the output terminal provided with the selector circuit. That is, the logic circuit constructed according to the present invention can effectively test all the output terminals using an inexpensive test device with a small number of test terminals even if the specification has many output terminals.

Hereinafter, the present invention will be specifically described with reference to the drawings. However, the following disclosure is merely an example of the present invention, and does not limit the technical scope of the present invention.

Embodiment FIG. 1 is a block diagram showing a configuration example near an output terminal of a logic circuit configured according to the present invention.

In the figure, output terminals 5 and 6 are output terminals for a logic signal 7 or 8 in this logic circuit, and are configured to output the logic signal 7 or 8 to the outside via an output buffer 1 or 4, respectively. ing.

Further, in this logic circuit, a selector circuit 3 is provided in a stage preceding the output buffer 4 of the output terminal 6. That is,
The output terminal 6 is configured to output the logic signal 8 to the outside via the selector circuit 3 and the output buffer 4. On the other hand, the output of the output buffer 1 at the output terminal 5 is connected to the input of the input buffer 2, and the output of the input buffer 2 is input to the selector circuit 3. The selector circuit 3 is configured to selectively output the output signal of the input buffer 2 and the logic signal 8 in response to the select signal 9.

In the logic circuit configured as described above, the logic signal 7 and the logic signal 8 can be selectively output from the output terminal 6 by controlling the selector signal 9. That is, when the test of this logic circuit is performed, if the number of test terminals of the test device is smaller than the number of output terminals of this logic circuit, only the output terminal 6 is connected to the test terminal, Signal 7 and logic signal 8 can be tested sequentially.

Thus, a logic circuit configured according to the present invention is:
The logic signals output to all the output terminals can be tested by a test device having a smaller number of test terminals than the number of its own output terminals.

Embodiment 2 FIG. 2 is a block diagram showing a configuration near an output terminal in another configuration example of a logic circuit configured according to the present invention.

In the figure, output terminals 20, 21 and 22 are output terminals of a logic signal 17, 18 or 19 in this logic circuit, and output a logic signal 17, 18 or 19 via an output buffer 10, 12 or 14, respectively. It is configured to output to the outside.

Further, in this logic circuit, the output buffer of the output terminal 22 is used.
The selector circuit 15 is provided in a stage preceding the selector 14. That is,
The output terminal 22 is configured to output the logic signal 19 to the outside via the selector circuit 15 and the output buffer 14. On the other hand, the output buffers 10 and
The output of 12 is connected to the input of an input buffer 11 or 13, respectively, and the output of the input buffer 11 or 13 is input to a selector circuit 15. Further, the selector circuit 15 is configured to selectively output one of the output signals of the input buffers 11 and 13 and the logic signal 8 by the select signal 16.

In the logic circuit configured as described above, the select signal
By controlling 16, the logic signal 17, 18 or 19 can be selectively output from the output terminal 22. That is, when the test of this logic circuit is performed, if the number of test terminals of the test device is smaller than the number of output terminals of this logic circuit, only the output terminal 22 is connected to the test terminal, and the select circuit 16 By switching the state of 15, the output terminal 22 can also test the logic signals 17 and 18 originally output to the output terminals 20 and 21.

As described above, in the logic circuit according to the present embodiment, one test terminal can test the logic signals of three output terminals.

As described above, the logic circuit according to the present invention includes a logic signal output terminal having a bidirectional buffer and a logic signal output terminal having a selector circuit connected to the input buffer side of the bidirectional buffer. By combining with
Multiple logic signals can be observed at one output terminal. Therefore, a logic circuit constructed according to the present invention is:
Even with specifications with many output terminals, all output terminals can be effectively tested using a low-cost test device with few test terminals, such as a 256-pin test device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration near an output terminal of a part of a logic circuit constructed according to the present invention. FIG. 2 is a block diagram showing a part of another embodiment of a logic circuit constructed according to the present invention. 3 is a block diagram showing a configuration near an output terminal of FIG. [Main reference numbers] 1, 4, 10, 12, 14 ... output buffer 2, 11, 13 ... input buffer 3, 15 ... selector circuit 5, 6, 20, 21, 22 ... output terminal 7, 8, 17, 18, 19 ... Logic signal 9, 16 ... Select signal

Claims (1)

(57) [Claims] 1. A semiconductor integrated logic circuit formed on a single chip, wired so that each of a plurality of logic signals is output from a corresponding one output terminal via a corresponding one output buffer. Wherein a signal line of a first logic signal is connected to an input of a corresponding first output buffer,
The output of the output buffer is connected to the corresponding first output terminal and also to the input of the input buffer, and the signal line of the second logic signal is connected to the first input of the selector circuit. The second input of the selector circuit is connected to the output of the input buffer, and the output of the selector circuit is connected to the input of a second output buffer corresponding to the signal line of the second logic signal. The output of the second output buffer is connected to a corresponding second output terminal. By controlling the selector circuit, the first logic signal and the second signal are output from the second output terminal. To selectively output any one of the logic signals of the first and second logic signals, and outputs the first logic signal to a first output buffer and a second output signal of the second logic signal.
A semiconductor integrated logic circuit characterized in that both output buffers can be tested simultaneously by outputting from said second output terminal via said output buffer.