JPS6295582A - Display control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention displays figures (hereinafter referred to as figures, including characters, symbols, and images) on a display device using a cathode ray tube or the like using a raster scan method. The present invention relates to a display control circuit for cases where

[Conventional technology]

FIG. 4 is a block diagram showing a conventional circuit. In the figure, (1) is an inverter circuit which generates an inverted signal of a horizontal synchronizing signal. (2) is a down counter with a preset terminal (parallel signal input terminal), which is referred to as a first down counter in this specification. Is (3) a state in which the count value of down counter (2) has reached O in the decoder? + (put out. (4)
is the first flip-flop, 15) is a NOR gate into which the output of the inverting output terminal Q of the flip-flop (4) and the horizontal synchronization signal are input, +61 is an oscillation circuit, and (7) is a down counter with a preset terminal. In this specification, it is referred to as the second down or counter.

(8) is a decoder that detects all states in which the count value of the town counter 17) becomes 0, and (9) is a second flip-flop. CK of down counter t21, +71 is a clock input terminal, PR is a preset signal input terminal,
D is a parallel signal input terminal, and Q is a parallel signal output terminal.

At the rising point of the signal at terminal PR, No. 1g, which is being pressed at terminal 1, is preset. S of flip-flops +41 and +91 is a set signal input terminal,
Rid II upper set number input terminal! llQ is a signal output terminal, and Ql is an inverted signal output terminal.

It works vaguely, and I get confused and try to explain it. Down counter (2)
This is used to determine the vertical display start position of a cathode ray tube, etc., and specifies, from the vertical synchronization signal, the position of the scanning line grain and whether to start displaying the square figure using vertical display position data. That is, the vertical direction display position data is preset by the vertical synchronization signal, and thereafter, the input signal of the terminal CK rises every time the horizontal synchronization signal falls, and the numerical value 1 is counted down. Decoder (3
) detects all the times when the count value of the down counter (2) reaches O and sets the flip-flop (4). When the flip-flop (4) is set, the outputs of the terminals become 'L' level, and during the period when the output of the terminal Q is at l L l level and the horizontal synchronizing signal is at lL level, the output from the NOR gate (5) is +1'H'. A level signal is output, enabling the oscillation circuit (6) to oscillate.The oscillation circuit (6N) generates a basic clock of a predetermined frequency while the output of the NOR gate (5) is at the lHl level.

The down counter (7) is used to completely determine the starting point of the horizontal display position, and the horizontal display position/q data is preset at the rising point of the horizontal synchronization signal, and the basic clock of the output of the oscillation circuit (6) is set. Each time the number is input, the number is counted down by one. The decoder (8) is a down counter (
The point where the count 1 of 7) becomes O is detected, the flip-flop (9) is set, and a display start signal sound <l is generated. The flip-flop (9) is reset at the rising point of the horizontal synchronization signal. After displaying several scanning lines depending on the size of the figure to be displayed, the flip-flop (
4) to stop the oscillation of the oscillation circuit (6).

[Problem that the invention seeks to solve]

The operation of the conventional circuit shown in FIG. 4 is shown in the operation time chart of FIG. The down counter (2) counts down the number 1 at the falling point of the horizontal synchronization signal, so this down count causes the down counter (2) to
The count value becomes 0, which is detected by the decoder (3), and upon this detection, the flip-flop (4) is set and the point at which its inverted output reaches the l L l level is slightly delayed from the falling point of the horizontal synchronizing signal. That is, in the first scanning line after the start of display, the rising point of the output of the NOR gate (5) is slightly delayed from the falling point of the horizontal synchronizing signal. On the other hand, since the Q output of the flip-flop (4) is already at l L level after the second grain of the running forest line, when the horizontal synchronizing signal falls, the output of the NOR gate (5) immediately rises. Therefore, for the first scanning line and the second and subsequent scanning lines, the time between the oscillation start point of the excavation circuit (6) and the falling point of the horizontal synchronizing signal is tl and t2 shown in FIG.
Different like.

FIG. 6 is a diagram showing an example of a display by the circuit shown in FIG. 4 (operation time chart shown in FIG.
This shows the problem that lines are displayed out of alignment.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a display control circuit that prevents display from being shifted by one scanning line.

[Means for solving problems]

In this invention, the first down counter is down-counted by the rising edge of the horizontal synchronization signal.

[Effect]

When the first down counter is counted down at the rising point of the horizontal synchronization signal, the point where the count value of the first down counter becomes 0 is detected, and after the first flip-flop is set, the horizontal synchronization signal is As a result, the output waveform of the NOR gate is the same for both the first scanning line and the second and subsequent scanning lines.

〔Example〕

All drawings of embodiments of this invention will be described below.

FIG. 1 is a block diagram showing one embodiment of the present invention.
The same reference numerals as those in the figures indicate the same or corresponding parts, and since they operate in the same way, duplicate explanations will be omitted. The difference between the circuit in Figure 1 and the circuit in Figure 4 is that at 1!11tc and g in Figure 1, there is no inverter (1), so the first down counter (2) is the rising point of the horizontal synchronization signal. It is counted down. Therefore, the output of the Q terminal of the flip-flop (4) becomes the IL level at a time a little delayed from the rising 9 point of the horizontal synchronizing signal, and at the falling point of the horizontal synchronizing signal, 1 is output from the flip-flop (4). The output of the Q terminal of is already lL level, so the NOR gate (
The output waveform of 5) is determined entirely by the waveform of the horizontal synchronizing signal, and therefore both the first scanning line and the second scanning line have the same waveform.

Fig. 2 is an operation time chart showing all the waveforms of each part in Fig. 1, and is displayed using the same display method as Fig. 5, but the difference from Fig. 5 is that t 1 = t 2. That's true.

Figure 3 is a diagram showing an example of the display by the circuit shown in Figure 1 (the operation time chart shown in Figure 2), and is displayed using the same display method as Figure 6, but unlike Figure 6. tl
= t2, the first scan line 1 in FIG.
The problem of lines being displayed out of alignment has been resolved.

〔Effect of the invention〕

As described above, according to the present invention, since the counting operation of the down counter for detecting the display position in the vertical direction is performed at the rising edge of the horizontal synchronization signal, the number of circuit components can be increased compared to the conventional circuit. It is possible to eliminate the disadvantage that the display is shifted by one line of the first scanning line.

[Brief explanation of drawings]

Is Figure 1 an example of this invention? 2 is an operation time chart showing the waveforms of each part in FIG. 1, and 3 is a block diagram shown in FIG.
Is the diagram an example of the display using the circuit in Figure 1? 4 is a block diagram showing a conventional circuit, FIG. 5 is an operation time chart showing waveforms of each part in FIG. 4, and FIG. 6 is an example of a display by the circuit in FIG. 4. Figure shown. (2) is the first down counter, +31U decoder, (
4) is a first flip-flop, 15Hj, NOR gate, (6) is an oscillation (lower) path, (7) is a second down counter, 18) is a decoder, and (9) is a second flip-flop. In addition, the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a display control circuit for displaying figures (including characters, symbols, and images) using a raster scan method, vertical display position data is preset by a vertical synchronization signal, and the vertical synchronization signal rises at the rising edge of the horizontal synchronization signal. A first down counter that counts down by 1 every time the count value of this first down counter reaches 0. A first flip-flop that is set when the count value of this first down counter becomes 0. When this first flip-flop is in a set state. An oscillation circuit that starts oscillation at the falling point of the horizontal synchronizing signal and generates a system clock of a predetermined frequency while the horizontal synchronizing signal is at "L" level, and horizontal display position data is generated at the rising point of the horizontal synchronizing signal. A second down counter that is preset and counts down by 1 every cycle of the system clock that is the output of the oscillation circuit, and is set when the count value of this second down counter reaches 0, and is set to count down the value of the horizontal synchronization signal. A display control circuit comprising: a second flip-flop that is reset at a rising time and whose setting time becomes a display start signal; and means for resetting the first flip-flop using a display end signal.