JPS5840707Y2 - television pattern signal generator - Google Patents

Description

[Detailed description of the invention] The present invention relates to a television pattern signal generator, which is a pattern signal generator for obtaining test pattern signals and other television signals for measuring the resolution of a television picture tube using a digital circuit. It is most suitable for use in vessels.

As a conventional pattern signal generator of this kind, a circuit shown in FIG. 1 is known.

When a pattern signal S as shown in FIG. 2 is obtained by this circuit, the following operation is performed.

That is, the pattern signal S shown in FIG. 2 is stored in the memory 1 in advance in a state divided by the pulse period of the clock pulse.

In this state, the address code is A.

When the address is specified by adding -A5, the pattern signal stored in the memory 1 is read out as outputs 01 to Oo, and this pattern signal is stored in the shift register 2.

In the shift register 2, the stored contents are sequentially shifted for each clock pulse supplied to the terminal 3, whereby a pattern signal S is obtained from the output terminal 4.

Therefore, when obtaining the pattern signal S shown in FIG. 2 using the circuit shown in FIG. 1 and shift register 2
is necessary.

The pattern signal S shown in Fig. 2 is shown as being divided into 24 parts, but in reality it is divided into 600 to several hundred parts, and a correspondingly large capacity memory 1 and shift register 2 are required. It ends up being expensive.

The present invention was devised in view of the above-mentioned problems, and includes a first counter that counts a predetermined number of clock pulses in each horizontal scanning section and forms scale information along the horizontal scanning line, and a memory that stores information on a plurality of rising and falling positions of a pattern signal for each horizontal scanning line; a coincidence detection circuit that detects substantial coincidence between the output of the first counter and the output of the memory; It is equipped with a flip-flop that is alternately set and reset for each output pulse of the detection circuit, and a second counter that counts the output pulses of the above-mentioned several-sheet output circuit for each horizontal scanning section, and the address of the memory is manually controlled. is supplied with first address information incremented for each horizontal scanning line, and second address information for sequentially reading out the plurality of rising and falling information in each scanning line is supplied to the second address information. A pattern signal corresponding to the memory contents is obtained from the output of the flip-flop.

With this configuration, it is possible to use a memory with a small capacity, thereby reducing costs.

Hereinafter, the present invention will be explained by way of examples with reference to FIGS. 3 and 4.

In FIG. 3, memory 1 is a so-called ROM (Read
Only Memory) and address code input A.

By adding -A4 and address codes A5 to A8 to specify an address, it is possible to obtain the signals stored at this address as outputs 01 to 05.

Outputs 01 to 05 are position information of rising and falling edges of the pattern signal.

Also address A. -A4 is given to designate the horizontal scanning line number, and addresses A5 to A8 are given to designate the reading order of the rising and falling position information of the pattern signal in each scanning line.

Address code input A. - A4 is, for example, a counter that counts the horizontal synchronizing signal from a television receiver as a clock pulse for receiving a television signal obtained using the pattern signal S, and uses the vertical synchronizing signal as a reset pulse. The output may be supplied.

The counter 5 receives the clock pulse P supplied to the CP terminal.
The count contents are output 0A.
- Obtained as OE.

Further, the count contents of the counter 5 are reset by supplying a signal to the reset terminal R.

The reset signal may be a horizontal reset signal synchronized with a horizontal synchronization signal supplied from the outside.

Outputs 01-05 of memory 1 and outputs 0A-OE of counter 5 are compared by exclusive OR circuits 11-14, respectively.

The outputs of the exclusive OR circuits 11 to 14 are NANDed by a five-man NAND circuit 15 and then supplied to a monomulti 16.

This monomulti 16 prevents malfunction of the circuit due to whisker-like noise that may occur during the access time until inputs A1 to A4 or inputs A5 to A8 of the memory 1 are changed to obtain a new output signal. non-retriggerable
There are many types of things.

The output of the monomulti 16 is supplied to a footflop 17 and a counter 18.

The flip-flop 17 is a normal flip-flop whose state is inverted when triggered by the falling edge of a pulse, and is reset for each horizontal scanning line by a horizontal reset pulse.

The counter 18 counts the number of pulses obtained from the monomulti 16, and its outputs P□-P4 are supplied to the memory 1 as inputs A5-A8.

As a result, a plurality of pieces of rising and falling position information of the pattern signal stored in the memory 1 are sequentially read out for each horizontal scanning line.

The counter 18 is reset every horizontal scan by a horizontal reset pulse.

Next, the operation for obtaining the pattern signal S shown in FIG. 4 using the above configuration will be explained with reference to FIG. 3.

Note that the signals a-s shown in FIG. 4 indicate the signals at each point in FIG. 3.

Input A to memory 1.

When specifying the address of the horizontal scan line by supplying -A4, first 0 is output as output 01 to 05 of memory 1.
1=1.02-0.03=1.04=1.05-■ (hereinafter simply written as (10111))
is obtained.

The outputs 01 to 05 (10111) have information indicating the position of the rising edge 6 of the pattern signal S.

On the other hand, the count output 0A-OE of the counter 5 compared in the exclusive OR circuits 10 to 14 is the output O□ to 05.
As shown in Figure 4, exclusive O
Outputs C, f, i, l of R circuits 10-14.

All O's are 1.

Furthermore, the above-mentioned complement relationship is OA = 01OB
= 1.0C = 0.0D = O, 0E = O is obtained from the counter 5, and this is the output of the counter 5.
is the time when two clock pulses p are counted.

Therefore, the signal q is obtained as the output of the NAND circuit 15,
This signal q is converted into a signal r by a monomulti 16.

This signal r causes the count output P1 of the counter 18 to
P4 is advanced to the next state and for this purpose inputs A5-A8 of memory 1 are changed to specify a new address.

As a result, outputs 01 to 05 become (10
011), but this output 01 to 05 (100
11) has information indicating the position of falling edge 7 of the pattern signal S.

In this case, the address is changed and the next output signal 01~0
During the access time until 5 appears, whisker-like noise may occur in the output O□~05.

Therefore, the inversion time τ of the monomulti 16 is set to be slightly longer than the time required to change the outputs O□ to 05 to prevent the above-mentioned whisker-like noise from being sent to the subsequent stage, thereby preventing malfunction of the circuit.

Outputs 01-05 of memory 1 are changed to (10011), and then outputs 0A-OE of counter 5 are changed to (011).
00), that is, when the counter 5 counts six clock pulses p, the output O□~05 and the output OA~
Since the relationship with OE is a complement, the exclusive OR circuit 10~
All fourteen output signals C, f, i, l, and 0 become 1.

Therefore, the output of the NAND circuit 15 changes to 0 and triggers the monomulti 16, and the signal r is obtained as its output.

By repeating the same operations as those described above, the signal r shown in FIG. 4 is obtained as the output of the monomulti 16.

When the flip-flop 17 is triggered by the fall of the signal r, a signal S is obtained as the output of the flip-flop 17.

Through the steps described above, a pattern signal corresponding to one scanning line forming a television image is obtained.

The counter 5 is reset by a signal synchronized with the horizontal synchronization signal, and the input A of the memory 1 is also input.

By sequentially repeating changing .about.A4 to an address from which a pattern signal corresponding to the next scanning line can be obtained, a pattern signal corresponding to each scanning line is sequentially obtained, thereby making it possible to form a television image.

Note that 8 bits are required as a scanning line address code to form a pattern on the entire screen.

As described above, according to the present invention, it is possible to use a memory with a small capacity and the number of words corresponding to the number of rising and falling positions of a pattern signal, and accordingly cost can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventionally known pattern signal generator;
Figure 2 is a waveform diagram showing the signals at each point in Figure 1;
4 is a circuit diagram showing a pattern signal generator according to the present invention, and FIG. 4 is a waveform diagram showing signals at each point in FIG. 3. In the symbols used in the drawings, 1 is a memory, 5 is a counter, 10, 11, 12, 13, and 14 are exclusive OR circuits, 15 is a NAND circuit, and 18 is a counter.

Claims (1)

[Scope of utility model registration request] Count a predetermined number of clock pulses for each horizontal scanning section,
a tenth counter that forms scale information along the horizontal scanning line; a memory that stores information on a plurality of rising and falling positions of the pattern signal to be formed for each horizontal scanning line;
a coincidence detection circuit that detects a substantial coincidence between the output of the first counter and the output of the memory; a flip-flop that is alternately set and reset for each output pulse of the coincidence detection circuit; and a second counter for counting the output pulses of the number counting circuit, and the address input of the memory is supplied with first address information that is incremented for each horizontal scanning line, and Second address information for sequentially reading out the plurality of rising and falling information on each scanning line is supplied from the second counter, and a pattern signal corresponding to the memory contents is obtained from the output of the flip-flop. A television pattern signal generator characterized in that: