JPS6322593B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to display devices such as character display devices and graphic display devices.

Conventional configuration and problems thereof Conventionally, in a display device such as a character display device, when displaying information stored in a display memory is arbitrarily divided on the display or scrolled vertically and horizontally, When re-editing the display memory through program processing or using registers corresponding to each line with a line-by-line counter, etc., the screen division positions are limited in advance by hardware, and in the former case, the processing speed
In the latter case, there were problems such as a lack of flexibility.

Purpose of the Invention The present invention realizes extremely flexible screen split display and full or partial scrolling in the vertical and horizontal directions with a small circuit configuration and easy program settings, and has flexibility in screen configuration that was lacking in conventional devices. The object of the present invention is to provide a display device that can obtain the following.

Structure of the Invention The present invention resets a counter each time a synchronization signal is switched in the horizontal and/or vertical direction, so that the screen division position can be easily changed and set. It has a register and a detector to detect the arbitrarily set value of this reference counter, and from the value detected by the detector, the address counter changes to the value stored in advance in the address update register. Furthermore, it has a register and a detector to detect the arbitrary setting value of the address counter, and the address counter is also set in the address update register in advance according to the value detected by the detector. With a configuration that allows the counting operation to continue from the memorized value,
The above objectives have been achieved.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

Vertical counter 1 is reset by vertical synchronizing signal VS, and outputs vertical count signal VC by counting horizontal synchronizing signal HS. The vertical address counter 2 counts the horizontal synchronizing signal HS from an arbitrary position in one vertical section, and stores it in the display memory 3.
Vertical address signal for reading the display memory 3 for reading out the contents of and displaying it on the display 4
Output VA. The register 10 is the display memory 3
Set an arbitrary value for the vertical address. register 2
0, register 30 and register 40 set arbitrary values for the vertical count signal VC. The arbitrary set values of these four types of registers are stored by data bus signals from the arithmetic and control unit 6. A detector 11 detects a match between the set value of the register 10 and the output of the vertical address signal VA. The detector 21 has a register 20
The set value of the register 30 and the vertical count signal VC, the detector 31 detects the set value of the register 30 and the vertical count signal VC,
The detector 41 detects coincidence between the set value of the register 40 and the vertical count signal VC. These four types of detectors output detection signals L1, L2, L3 and L4, respectively. Address update register 1
2. Address update register 22, address update register 32, and address update register 42 are stored by data bus signals from arithmetic and control unit 6. These four types of address update registers are for updating the address count value of the vertical address counter 2, and are for each detection signal L1, L2,
It is read by L3 and L4 and loaded into vertical address counter 2 to update its value.
NOR gate 5 uses detection signals L1, L2, and L when reading the set values of these four types of address update registers.
3 and L4 are input, and a load signal LS is output.

FIG. 2 shows an example of a timing chart of the vertical synchronizing signal VS, horizontal synchronizing signal HS, and load signal LS.

An example of operation will be described below with reference to FIG. An arbitrary display start position uniquely determined by the vertical counter 1 is set in the register 20, and an address to be read from the display memory 3 at the time of display start is set in the address update register 22. The count position of the vertical counter at which the screen is to be divided is set in the registers 30 and 40, and the address of the display memory 3 to be read at the screen division position is set in the address update register 32 and the address update register 42, respectively. Further, at the same time as writing an arbitrary set value for changing the address using an arbitrary output value of the vertical address counter 2 into the register 10, the address update register 12 sets the address to be updated.

FIG. 3 shows the display memory and display screen that are read out for display with this setting. In Figure 3, L
2C, L3C and L4C are determined by the output value of the vertical counter 1, and can be set in units of one horizontal synchronizing signal, or in other words, one line, and the address of the display memory 3 can be updated arbitrarily. L1
C is determined by the output value of an arbitrary address of the vertical address counter 2, and is not uniquely determined within the vertical section. If the screen shown from the L3C position is now scrolled, the set value of the address update register 32 may be gradually changed by the arithmetic and control unit 6. Also, the fourth
As shown in the figure, the first address read by the LS load signal and any second address read depending on this address read are set in the register 10 and in the address update register 12. If an address located between the first address and the second address is set, a plurality of L1C points will be displayed.

Next, the set value of the register 10 is set to be the same as the set value of the address update register 32, and the set value of the address update register 12 is set to the address update register 32.
When the setting value is set to be the same as that of , and the setting value is increased sequentially, the contents of the same address are repeatedly read from the display memory as shown in FIGS. 5, 6, 7, and 8. An effect similar to forming a single display screen can be obtained.

Although only the vertical synchronization system has been described to simplify the explanation, the same effect can be obtained with a similar configuration for the horizontal synchronization system.

Effects of the Invention According to the present invention, each counter group is reset and counted every vertical and/or horizontal synchronization period, and the address counter group starts counting from an arbitrary value of the output of the counter group. It also has a register group and a detector group to enable arbitrary setting and detection of the respective output values of the counter group and the address counter group, and the output value of each of the counter group and address counter group can be arbitrarily set and detected. Since the configuration is such that it is possible to load an updated address into each address counter from a register that stores address load data for which a value has been set, any arbitrary value uniquely determined by a synchronization signal can be used. Data from any address in the display memory can be displayed at any position, and the address for reading the display memory can be switched at any position.

It is possible to divide the screen so that an arbitrary number of addresses can be read out at any arbitrary position on the display screen, and so-called partial scroll display of only an arbitrary section from an arbitrary position is possible.

Since the arbitrary value of the address counter can be updated to the detected arbitrary address, the display memory can be used in a loop, and special effects can be displayed.

It is possible to obtain extremely excellent effects such as
At the same time, it is possible to reduce the program load on the arithmetic and control unit for displaying the screen, and furthermore, it has the advantage that the screen can be easily switched in an extremely short time.

In the description of the present invention, the case where the display screen is composed of horizontal scanning lines has been described as an example, but the same effect can be obtained when the display screen is composed of vertical scanning lines. Needless to say, these are included in the present invention.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
The figure shows a timing chart of a horizontal synchronization signal, a vertical synchronization signal, and a load signal. Examples of display sections, FIGS. 5, 6, 7 and 8, show special effects obtained by combining the set values of registers and address update registers in the configuration of an embodiment of the present invention. It is a figure which shows the example of a screen display. 1... Vertical counter, 2... Vertical address counter, 3... Display memory, 6... Arithmetic control unit, 10, 20, 30, 40... Register, 1
1, 21, 31, 41...detector, 12, 22,
32, 42...Address update register.

Claims (1)

[Claims] 1 A display device that reads out information stored in a display memory in synchronization with a synchronization signal using a raster scan method and displays it on a display such as a cathode ray tube, which includes a horizontal counter and a horizontal address counter counted by a display clock signal; A register and a detector for setting and detecting an arbitrary output value of the counter, a register and a detector for setting and detecting an arbitrary output value of the horizontal address counter, and the horizontal address when the set value is detected. A horizontal synchronization system screen division means consisting of a horizontal address update register that updates the counting start value of the counter, a vertical counter and a vertical address counter that count based on the horizontal synchronization signal, and for setting and detecting an arbitrary output value of the vertical counter. a register and a detector for setting and detecting an arbitrary output value of the vertical address counter; a vertical address update register that updates the counting start value of the vertical address counter when the set value is detected; 1. A display device comprising at least one of vertical synchronization screen dividing means.