JPS6293760A - Arrangement improving device - Google Patents

Abstract

PURPOSE:To easily design a substrate by which a signal delay becomes a problem, by providing a means for recognizing the increase of a signal delay caused by an arrangement exchange, and executing a parts arrangement exchange by which the sum total of a virtual wiring length is small and also the signal delay becomes small. CONSTITUTION:An arrangement improvement control part 11 starts an arrangement exchange candidate generating part 14 when the processing of an initial virtual wiring length setting part 13 is ended, starts a virtual wiring length sum total calculating part 15 when the processing of the generating part 14 is ended, starts a signal delay increase calculating part 16 when the sum total of the virtual wiring length is decreased, and starts an arrangement exchange candidate generating part 14 when said sum total is not decreased. The signal delay increase calculating part 16 derives a virtual wiring length at every signal line by referring to a parts arrangement candidate table 12d and the parts inter-terminal connection table 12b of a memory table 12, and derives the existence of the increase of a signal delay, from said value and the value of the corresponding signal line of an initial virtual wiring length table 12c of the memory table 12. When the signal delay is not increased, a wiring exchange part 17 is started, and the parts arrangement information of the parts arrangement candidate table 12d is set to the parts arrangement table 12a of the memory table 12.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a layout improvement device used for layout design of printed wiring boards, jet collector circuits, and the like.

``Prior art'' Conventionally, this type of placement improvement device has determined whether or not to perform placement exchange only based on an increase or decrease in the total virtual wiring length, and does not take into account increases or decreases in the virtual wiring length of individual signal lines. There wasn't. Documents related to conventional examples include: 1. CAD for logic devices (Information Science Society of Japan); 2. CAD for “a'f-circuits” (City T-
ii'fi fiii academic society), etc.

``Problem that ROBOT attempts to solve'' The conventional placement improvement device mentioned in I7 above evaluates only the increase or decrease in the total virtual wiring length, without considering the increase or decrease in the virtual wiring length of each individual signal line. Therefore, in general, after placement^-improvement, the total virtual wiring length decreases, but the virtual wiring length increases for each individual signal line, and the Because of the existence of such bases, signal delay becomes a problem (on the contrary, it is difficult to improve the layout using improved equipment for Jin-5).

``Means for Solving Problems'' This invention is a placement improvement device that exchanges the placement of parts on a plate so that the sum of the virtual wiring lengths based on the terminal positions to be connected is reduced. Provide means for recognizing increases in signal delay. When the total virtual wiring length decreases during the process of placement exchange, the signal delay increase calculation means is activated, and if there is an increase in signal delay, placement exchange candidates are determined again, and if there is no increase in signal delay, placement exchange is performed. In this way, it is possible to perform component placement exchange that reduces the total virtual wiring length and reduces signal delay.

"Example" Next, the present invention will be explained with reference to the drawings.

Figure 1 is a block diagram showing an embodiment of the present invention.
Arrows marked with solid lines indicate the flow of data, and arrows marked with broken lines indicate the flow of control. The placement improvement control unit 11 first inputs component placement information and component terminal connection information to the input terminal IRI.
It is input from O and set in the component arrangement table 12a and the component terminal connection table 12b of the memory table 12. Next, the placement improvement control unit 11 initializes the initial virtual wiring length setting unit 1.
Start 3. The initial virtual wiring length setting unit 13 refers to the component arrangement table 12a and the component terminal connection table 12b of the memory table 12 to obtain the virtual wiring length for each signal line, and sets it in the initial virtual wiring length table 12C of the memory table 12. do.

The placement improvement control section 11 activates the placement exchange candidate generation section 14 when the processing of the initial virtual wire length setting section 13 is completed. The placement exchange candidate generation unit 14 generates a component placement table 12a and a component terminal connection table 12b of the memory table 12.
Referring to
Set to 2d. The arrangement improvement control unit 11 performs arrangement, arrangement exchange (
When the processing by the one-line complement generation unit 14 is completed, the virtual wire length sum calculation unit 15 is activated. Virtual wiring length total calculation unit 15
are the component placement table 12a, component placement candidate table 12d, and component terminal connection table 1 of the memory table 12.
2b, the total sum of virtual wiring lengths for the current component placement and the total sum of virtual wiring lengths for component placement candidates are obtained, and each length is passed to the placement improvement control/distribution section 11.

When the processing of the virtual wire length sum calculation section 15 is completed, the placement improvement control section 11 activates the signal delay increase calculation section 16 if the sum of the virtual wire lengths is decreasing, and if it is not decreasing, it activates the signal delay increase calculation section 16. Activate the placement exchange candidate generation unit 1.1.

The signal delay increase calculation unit 16 uses the component placement candidate table 12d of the memory table 12 and the component terminal connection table 12.
Determine the (anti-imaginary wiring length) for each signal line by referring to b, and calculate the value and the initial virtual wiring length table 12C of the memory table 12.
The presence or absence of an increase in signal delay is determined from the value of the corresponding signal line, and is passed to the placement improvement control unit 11.

When the processing of the signal delay tank jJO calculation unit 16 is completed, the placement improvement control unit 11 starts the placement exchange unit 17 if the signal delay has not increased, and starts the placement exchange unit 17 if the signal delay has increased. 14. The placement exchange unit 17 sets the component placement information of the component placement candidate team 12d in the memory table 12 in the component placement table 12a of the memory table 12. The placement improvement control section 11 activates the placement exchange candidate generation section 14 when the processing of the placement exchange section 17 is completed.

When the placement exchange unit 17 is not activated within a predetermined number of repetitions during the repeated activation of the placement exchange candidate generation unit 14, the placement improvement control unit 11 interrupts the repetitive processing and updates the component placement table in the memory table 12. The component placement information of 12H is outputted to the output means 18, and the process ends.

``Effects of the Invention'' As explained above, the present invention has the effect that it is possible to easily design a board in which signal delay is a problem because the placement is exchanged while recognizing the increase in signal delay due to placement exchange. There is.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. 10: Human power means, 11: Placement improvement control section, 12: Memory table, 13: Initial virtual wire length setting section, 14: Placement exchange candidate generation section, 15: Temporary black wire length sum calculation section, 16:
Signal delay increase 110 calculation section, 17: Placement exchange section, 18: Output means.

Claims (1)

[Claims] (1) Component placement information storage means, component terminal connection information storage means, component placement candidate storage means, initial virtual wiring length information storage means, and input component placement information and component terminal connection information from the outside. Initial setting means stored in the component placement information storage means and component terminal connection information storage means, and initial virtual wiring length information for each signal line from each storage information of the component placement information storage means and component terminal connection information storage means. an initial virtual wire length setting means for determining and storing this in the initial virtual wire length information storage means; and a component to be the object of placement exchange based on the stored information of the component placement information storage means and the component terminal connection information storage means. a placement exchange candidate generation means for determining and storing this as component placement candidate information in the component placement candidate information storage means; and each of the component placement information storage means, the component placement candidate information storage means, and the component terminal connection information storage means. virtual wiring length sum calculation means for calculating virtual wiring length summation information corresponding to the component placement information and virtual wiring length summation information corresponding to the component placement candidate information from the stored information; and between the component placement candidate information storage means and the component terminals. Signal delay increase calculation means for calculating signal delay increase information corresponding to an increase in virtual wire length for each signal line from each storage information of the connection information storage means and the initial virtual wire length storage means. a placement exchange means for storing stored component placement information in the component placement candidate information storage means in the component placement information storage means; a component placement information outputting device for outputting the stored component power distribution information in the component placement information storage means to the outside; The initial virtual wiring length setting means and the placement exchange candidate generation means are activated, and then the virtual wiring length sum calculation means is activated, and when the virtual wiring length summation of the component placement candidates is smaller, the signal delay increases. The calculation means is activated, and if the total virtual wiring length of the component placement candidates has not decreased, the placement exchange generation means is activated, and the signal delay as a result of calculation by the signal delay increase calculation means is increased. Activate the placement exchange candidate generating means when the signal delay is not increasing, activate the placement exchange means when the signal delay is not increasing, and activate the component placement information output means when the placement exchange means is no longer activated. Arrangement improvement device with control means.