JPH05206276A - Pattern forming device - Google Patents
Pattern forming deviceInfo
- Publication number
- JPH05206276A JPH05206276A JP4014767A JP1476792A JPH05206276A JP H05206276 A JPH05206276 A JP H05206276A JP 4014767 A JP4014767 A JP 4014767A JP 1476792 A JP1476792 A JP 1476792A JP H05206276 A JPH05206276 A JP H05206276A
- Authority
- JP
- Japan
- Prior art keywords
- line width
- wiring
- current
- current consumption
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路の配線
の適切な線幅を算出して自動配線を行い、半導体集積回
路のレイアウト図を作成するパターン生成装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generating apparatus for calculating an appropriate line width of a wiring of a semiconductor integrated circuit and performing automatic wiring to create a layout diagram of the semiconductor integrated circuit.
【０００２】[0002]
【従来の技術】半導体集積回路チップ（以下、ICチップ
と略記する）の配線に用いられる金属としてはAlが代表
的であるが、従来では、Al配線の線幅を設計者が決定し
ていた。以下に、Al線幅を決定する従来の方法を説明す
る。なお、図１は従来の方法によって設計者が決定した
配線幅で作成されたICチップのレイアウトの一部を示す
平面図である。図中、12，13及び14はそれぞれ回路ブロ
ック（以下、セルという）であって、セル12，13及び14
は電源線（以下、 VDD線という）30とグランド線（以
下、 GND線という）31とによって結線されている。ま
た、32，33及び34はそれぞれセル12，13及び14の VDD端
子、35，36及び37はそれぞれセル12，13及び14のGND 端
子であって、38及び39はセル13及び14へのVDD線30の分
岐点、40及び41はセル13及び14への GND線31の分岐点を
示す。2. Description of the Related Art Al is a typical metal used for wiring of a semiconductor integrated circuit chip (hereinafter abbreviated as IC chip), but conventionally, a designer has determined the line width of the Al wiring. .. A conventional method for determining the Al line width will be described below. Note that FIG. 1 is a plan view showing a part of the layout of an IC chip created with a wiring width determined by a designer by a conventional method. In the figure, 12, 13, and 14 are circuit blocks (hereinafter, referred to as cells), which are cells 12, 13, and 14, respectively.
Are connected by a power supply line (hereinafter, V DD line) 30 and a ground line (hereinafter, GND line) 31. Also, 32, 33 and 34 are V DD terminals of cells 12, 13 and 14, 35, 36 and 37 are GND terminals of cells 12, 13 and 14, respectively, and 38 and 39 are to cells 13 and 14, respectively. V DD line 30 branch points, 40 and 41 denote GND line 31 branch points to cells 13 and 14, respectively.
【０００３】設計者は、例えば各セル12，13，14の動作
時における平均消費電流値を、各セル12， 13 ，14の消
費電流の一定値として、それぞれａ，ｂ，ｃと見積も
る。見積もった平均消費電流値とAl線の膜厚及び許容最
大電流密度とから各 VDD端子32，33，34の必要線幅をそ
れぞれＡ，Ｂ，Ｃと算出する。次に、各 VDD端子32，3
3，34の結線関係を考慮し、下流のセルの消費電流を上
乗せした電流値に基づいて各分岐点における VDD線30の
線幅を決定する。即ち、分岐点38では VDD線30がVDD端
子32及び33へ分岐しているので、分岐点38における VDD
線30の線幅は（Ａ＋Ｂ）となる。同様に、分岐点39にお
ける VDD線30の線幅は（Ａ＋Ｂ＋Ｃ）となる。 GND線31
の線幅も同様の方法で求める。The designer estimates, for example, the average current consumption values of the cells 12, 13, and 14 during operation as a, b, and c, which are the constant values of the current consumption of the cells 12, 13, and 14, respectively. The required line widths of the V DD terminals 32, 33, and 34 are calculated as A, B, and C, respectively, from the estimated average current consumption value, the film thickness of the Al wire, and the maximum allowable current density. Next, each V DD pin 32, 3
The line width of the V DD line 30 at each branch point is determined based on the current value obtained by adding the current consumption of the downstream cells in consideration of the connection relationship between 3 and 34. That is, since V DD line 30 at the branch point 38 is branched to V DD terminal 32 and 33, V DD at the branch point 38
The line width of the line 30 is (A + B). Similarly, the line width of the V DD line 30 at the branch point 39 is (A + B + C). GND wire 31
The line width of is also obtained by the same method.
【０００４】[0004]
【発明が解決しようとする課題】ところで、集積回路の
消費電流値はその動作時間の経過に伴って刻々と変化す
るものであって、例えば下流に接続されているセルが上
流のセルと同時に動作しない動作モードの場合、どの分
岐点における配線幅も下流の分岐先のセルでの消費電流
を上乗せして画一的に算出する従来のような方法では、
線幅が必要以上に太い分岐点が存在するのでチップサイ
ズが大型化するという問題がある。By the way, the current consumption value of an integrated circuit changes momentarily with the lapse of its operating time. For example, a cell connected to the downstream side operates simultaneously with an upstream cell. In the non-operating mode, the conventional method of uniformly calculating the wiring width at any branch point by adding the current consumption in the cell at the downstream branch destination,
There is a problem that the chip size becomes large because there is a branch point whose line width is thicker than necessary.
【０００５】また、誤って集積回路の消費電流を少なく
見積もった場合、金属線に許容最大電流密度を超える電
流が流れ、エレクトロマイグレーションによって金属線
が断線する可能性がある。If the current consumption of the integrated circuit is estimated to be low by mistake, a current exceeding the maximum allowable current density may flow in the metal wire, and the metal wire may be broken due to electromigration.
【０００６】さらに、ICチップの高集積化, 回路機能の
複雑化に伴って大規模化, 複雑化する回路設計におい
て、ますます最適な線幅での設計が必要となるが、設計
者の見積りに頼る従来の方法では線幅算出に要する時間
が増加するばかりで、限られた設計納期内に最適な線幅
を算出することが難しい。Furthermore, in the circuit design which becomes large in scale and becomes complicated with the high integration of IC chips and the complicated circuit functions, it is necessary to design with more and more optimum line width. With the conventional method relying on (1), the time required for line width calculation only increases, and it is difficult to calculate the optimum line width within the limited design delivery time.
【０００７】本発明はこのような問題点を解決するため
になされたものであって、集積回路の動作時間の経過に
応じた各セルの消費電流に基づいて配線幅を決定するこ
とにより必要十分な配線幅を自動的に求めるパターン生
成装置の提供を目的とする。The present invention has been made to solve such a problem, and is necessary and sufficient by determining the wiring width based on the current consumption of each cell according to the elapsed operating time of the integrated circuit. An object of the present invention is to provide a pattern generation device that automatically obtains a wide wiring width.
【０００８】[0008]
【課題を解決するための手段】本発明のパターン生成装
置は、集積回路の回路動作の経過に即した動作モード，
動作時間等ごとの各セルの消費電流に基づき、各セルの
動作タイミングに応じた必要十分な配線幅を決定するこ
とを特徴とする。SUMMARY OF THE INVENTION A pattern generating apparatus according to the present invention has an operation mode according to the progress of circuit operation of an integrated circuit,
It is characterized in that the necessary and sufficient wiring width corresponding to the operation timing of each cell is determined based on the current consumption of each cell for each operation time and the like.
【０００９】[0009]
【作用】本発明のパターン生成装置は、集積回路を構成
する各セルの消費電流を、この集積回路の動作モード，
動作時間等ごとに算出し、このセルごとの消費電流から
求まる各セルの各端子を流れる電流値と配線に用いる導
体の膜厚，許容最大電流密度等の電気的特性に関わるデ
ータとに基づいて各端子に必要な配線幅を算出し、動作
時間の所定時間単位ごとの各セルの消費電流と各端子に
必要な配線幅と電流の流れにおける始端，終端，上流，
下流等の各端子の位置関係のデータとに基づいて、端子
の結線関係及び動作モード，動作時間等ごとの各セルの
消費電流に即した配線の必要線幅を算出し、この必要線
幅を配線に用いる導体の加工可能な最小線幅以上の値に
補正して配線幅を決定し、線幅決定部により決定された
配線幅に基づくデータを装置外部へ出力するとともに決
定された配線幅でパターンを生成する。The pattern generating apparatus of the present invention determines the current consumption of each cell constituting the integrated circuit by the operation mode of the integrated circuit,
Calculated for each operation time, etc., and based on the current value flowing through each terminal of each cell obtained from the current consumption of each cell and the data related to the electrical characteristics such as the film thickness of the conductor used for wiring and the allowable maximum current density The wiring width required for each terminal is calculated, and the current consumption of each cell for each predetermined time unit of operation time and the wiring width required for each terminal and the beginning, end, upstream of the current flow,
Based on the positional relationship data of each terminal such as downstream, calculate the required line width of the wiring according to the terminal connection relationship and the current consumption of each cell for each operation mode, operation time, etc. The wiring width is determined by correcting it to a value equal to or greater than the minimum processable line width of the conductor used for wiring, and the data based on the wiring width determined by the line width determination unit is output to the outside of the device and the determined wiring width is used. Generate a pattern.
【００１０】[0010]
【実施例】以下、本発明をその実施例を示す図面に基づ
いて説明する。図２は本発明の配線パターン生成装置の
構成を示すブロック図である。図中１は集積回路の動作
モード又は動作時間ごとの各セルの消費電流値を算出す
る消費電流算出部である。消費電流記憶部２は、消費電
流算出部１が算出した各セルの消費電流値から求まる各
セルの端子ごとの消費電流値を記憶する。プロセスパラ
メータ格納部３は、Al線の膜厚、許容最大電流密度等の
電気的特性に関わるデータ及び加工可能な最小線幅を格
納している。前記端子配線幅算出部である必要線幅算出
前処理部４は、消費電流記憶部２及びプロセスパラメー
タ格納部３に記憶されているデータを用いて各端子に必
要な金属線幅を算出する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. FIG. 2 is a block diagram showing the configuration of the wiring pattern generation device of the present invention. In the figure, reference numeral 1 denotes a current consumption calculation unit for calculating the current consumption value of each cell for each operation mode or operation time of the integrated circuit. The current consumption storage unit 2 stores the current consumption value for each terminal of each cell, which is obtained from the current consumption value of each cell calculated by the current consumption calculation unit 1. The process parameter storage unit 3 stores data relating to electrical characteristics such as the film thickness of the Al wire, the maximum allowable current density, and the minimum workable wire width. The required line width calculation preprocessing unit 4, which is the terminal wiring width calculation unit, calculates the metal line width required for each terminal using the data stored in the consumed current storage unit 2 and the process parameter storage unit 3.
【００１１】位置・形状記憶部５は各端子の分岐状態を
示す結線形状及び電源供給側である上流の端子，最下流
の電源消費最終端の端子等の電流の流れにおける端子の
位置関係を記憶している。必要線幅算出部６は消費電流
算出部１，必要線幅算出前処理部４及び位置・形状記憶
部５のデータを用いて、集積回路の動作モード又は動作
時間ごとの各セルの消費電流及び端子の接続関係を考慮
した必要線幅を算出する。線幅決定部７は必要線幅算出
部６が算出した線幅データをプロセスパラメータ格納部
３に格納されている最小線幅データ以上の値に補正して
金属線幅を決定する。グラフィック表示部10は、線幅決
定部７により線幅が決定された配線の画像及び線幅の数
値を表示する。パターン生成部11は線幅決定部７が決定
した線幅データを用いて配線パターンを生成する。The position / shape storage unit 5 stores the connection shape indicating the branched state of each terminal and the positional relationship of the terminals in the current flow such as the upstream terminal on the power supply side and the terminal at the most downstream end of power consumption. is doing. The necessary line width calculation unit 6 uses the data of the current consumption calculation unit 1, the necessary line width calculation preprocessing unit 4 and the position / shape storage unit 5 to calculate the current consumption of each cell for each operation mode or operation time of the integrated circuit. Calculate the required line width considering the connection relationship of terminals. The line width determination unit 7 determines the metal line width by correcting the line width data calculated by the required line width calculation unit 6 to a value equal to or larger than the minimum line width data stored in the process parameter storage unit 3. The graphic display unit 10 displays an image of the wiring whose line width is determined by the line width determination unit 7 and a numerical value of the line width. The pattern generation unit 11 uses the line width data determined by the line width determination unit 7 to generate a wiring pattern.
【００１２】また、線幅比較部９は、人手により配線幅
が見積もられた実際の線幅データ８と線幅決定部７が決
定した金属線幅とを比較し、比較の結果、線幅に過不足
があった場合、その過不足があった部分の画像及び線幅
の数値をグラフィック表示部10に表示する。Further, the line width comparison unit 9 compares the actual line width data 8 in which the wiring width is manually estimated with the metal line width determined by the line width determination unit 7, and as a result of the comparison, the line width is calculated. If there is an excess or deficiency, the image of the portion with the excess or deficiency and the numerical value of the line width are displayed on the graphic display unit 10.
【００１３】以上のような構成のパターン生成装置によ
り VDD線の配線幅を決定する動作について説明する。な
お、図３は本発明のパターン生成装置により生成された
ICチップのパターンの一部を示す平面図である。図中、
12，13及び14はそれぞれセルであって、セル12，13及び
14は VDD線15と GND線16とによって結線されている。1
7，18及び19はセル12，13及び14の VDD端子、20，21及
び22はセル12，13及び14の GND端子、23及び24はセル13
及び14への VDD線15の分岐点、25及び26はセル13及び14
への GND線16の分岐点を示す。The operation of determining the wiring width of the V DD line by the pattern generation device having the above-mentioned configuration will be described. Note that FIG. 3 is generated by the pattern generation device of the present invention.
It is a top view showing a part of pattern of an IC chip. In the figure,
12, 13 and 14 are cells, respectively, and cells 12, 13 and
14 is connected by V DD line 15 and GND line 16. 1
7, 18 and 19 are V DD terminals of cells 12, 13 and 14, 20, 21 and 22 are GND terminals of cells 12, 13 and 14, and 23 and 24 are cells 13
V DD line 15 branch points to and 14 and 25 and 26 are cells 13 and 14
Shows the junction of GND line 16 to.
【００１４】また、図４は、図３に示すICチップの各セ
ル12，13，14の実動作による消費電流の波形及び動作タ
イミングを示すタイミングチャートである。図におい
て、ａ，ｂ，ｃはそれぞれ各セル12，13，14の動作時に
おける平均電流値である。なお、各セル12，13，14の動
作時の平均電流値ａ，ｂ，ｃにはａ＞ｂ，ａ＞ｃの関係
があるものとする。FIG. 4 is a timing chart showing waveforms and operation timings of current consumption by actual operation of each cell 12, 13, 14 of the IC chip shown in FIG. In the figure, a, b, and c are average current values when the cells 12, 13, and 14 are operating, respectively. It is assumed that the average current values a, b, and c of the cells 12, 13, and 14 during operation have a relation of a> b and a> c.
【００１５】第１段階では、各セル12，13，14の消費電
流を集積回路の動作モード又は動作時間ごとに算出す
る。算出方法としては、回路設計者による算出，回路シ
ミュレーションによる算出又は論理シミュレーションに
よる算出方法が可能である。これにより得られた、図４
に示すごとき動作時間ごとの消費電流の波形を消費電流
算出部１が記憶する。In the first stage, the current consumption of each cell 12, 13, 14 is calculated for each operation mode or operation time of the integrated circuit. The calculation method can be a calculation by a circuit designer, a calculation by circuit simulation, or a calculation method by logic simulation. Fig. 4 obtained by this
The consumption current calculation unit 1 stores the waveform of the consumption current for each operation time as shown in FIG.
【００１６】第２段階では、消費電流算出部１に記憶さ
れている波形データから求まる各セル12，13，14の消費
電流を、 VDD端子17，18，19ごとに消費電流記憶部２に
記憶する。なお、本実施例では、各セル12，13，14の消
費電流値として、図４にａ，ｂ，ｃで示すごとき動作時
の平均電流値を採用する。At the second stage, the consumption current of each cell 12, 13, 14 obtained from the waveform data stored in the consumption current calculation unit 1 is stored in the consumption current storage unit 2 for each V DD terminal 17, 18, 19. Remember. In this embodiment, as the current consumption value of each cell 12, 13, 14, the average current value during operation as shown by a, b, c in FIG. 4 is adopted.
【００１７】第３段階では、必要線幅算出前処理部４
が、消費電流記憶部２に VDD端子17，18，19ごとに記憶
されている各セル12，13，14の消費電流値とプロセスパ
ラメータ記憶部３に格納されているAl線の膜厚及び許容
最大電流密度の電気的特性データとを用いて、各 VDD端
子17，18，19に必要な VDD線幅を、（必要線幅）＝（各
端子を流れる電流値）／（Al線の許容最大電流密度）×
（Al線の膜厚）の計算式を用いて算出するとともに算出
結果を記憶する。なお、本実施例では、算出の結果得ら
れた各 VDD端子17，18，19に必要な VDD線幅を各々Ａ，
Ｂ，Ｃとする。In the third stage, the necessary line width calculation preprocessing unit 4
However, the consumption current value of each cell 12, 13, 14 stored in the consumption current storage unit 2 for each V DD terminal 17, 18, 19 and the film thickness of the Al wire stored in the process parameter storage unit 3 and Using the electrical characteristic data of the maximum allowable current density, determine the V DD line width required for each V DD pin 17, 18, 19 as follows: (required line width) = (current value flowing through each pin) / (Al line Maximum allowable current density) x
The calculation result is stored using the calculation formula of (Al film thickness). In this embodiment, the V DD line widths required for the respective V DD terminals 17, 18 and 19 obtained by the calculation are A,
B and C.
【００１８】第４段階では、必要線幅算出部６が、必要
線幅算出前処理部４に記憶されている各 VDD端子17，1
8，19の VDD線幅のデータと、位置・形状記憶部５に記
憶されているこれらの結線関係のデータと、消費電流算
出部１に記憶されているデータとを用いて、各 VDD端子
17，18，19間の結線関係を考慮した VDD線15の必要線幅
を分岐点23，24ごとに算出する。なお、位置・形状記憶
部５には VDD線15が分岐点24において VDD端子19へ分岐
し、分岐点23で VDD端子18に分岐した後、 VDD端子17で
最終端になるというデータが格納されている。At the fourth stage, the required line width calculation unit 6 causes the V DD terminals 17, 1 stored in the required line width calculation preprocessing unit 4 to be stored.
By using the data of the V DD line widths of 8 and 19, the data of the connection relations stored in the position / shape storage unit 5, and the data stored in the consumption current calculation unit 1, each V DD Terminal
Calculate the required line width of the V DD line 15 for each branch point 23, 24, taking into account the connection relationship between 17, 18, and 19. In the position / shape memory unit 5, the V DD line 15 branches to the V DD terminal 19 at the branch point 24, branches to the V DD terminal 18 at the branch point 23, and then becomes the final end at the V DD terminal 17. The data is stored.
【００１９】即ち、分岐点23においては VDD端子17，18
が合流しており、 VDD端子17，18に必要な VDD線幅は各
々Ａ，Ｂであって、セル12とセル13とは同時刻には動作
しないというデータから、分岐点23における VDD線幅
は、セル12とセル13とを比較して消費電流値が大きい方
のセル12の線幅であるＡとなる。同様に、分岐点24の V
DD線幅は、セル12，13，14が同時刻に動作しないという
データから消費電流値が最も大きいセル12の線幅である
Ａとなる。That is, at the branch point 23, V DD terminals 17 and 18
, And the required V DD line widths for V DD terminals 17 and 18 are A and B, respectively, and the data that cell 12 and cell 13 do not operate at the same time The DD line width is A, which is the line width of the cell 12 having the larger current consumption value when the cells 12 and 13 are compared. Similarly, V at branch point 24
The DD line width is A, which is the line width of the cell 12 having the largest current consumption value from the data that the cells 12, 13, and 14 do not operate at the same time.
【００２０】第５段階では、線幅決定部７が、必要線幅
算出部６で算出された分岐点23，24ごとの VDD線幅のう
ち、プロセスパラメータ格納部３に格納されている加工
可能な最小線幅に満たない VDD幅を適切な値に補正して
VDD線15の線幅を決定する。同様の方法で GND線16につ
いても適切なAl線幅を決定する。グラフィック表示部10
は、線幅決定部７により線幅が決定された配線の画像及
び線幅の数値を表示し、パタン生成部11は、線幅決定部
７により決定されたデータを用いてパターンを生成す
る。In the fifth step, the line width determining unit 7 processes the V DD line widths calculated by the necessary line width calculating unit 6 for each of the branch points 23 and 24 and stored in the process parameter storage unit 3. Correct the V DD width that is less than the minimum possible line width to an appropriate value.
Determine the line width of V DD line 15. Determine the appropriate Al line width for the GND line 16 in the same way. Graphic display 10
Displays the image of the wiring whose line width has been determined by the line width determination unit 7 and the numerical value of the line width, and the pattern generation unit 11 generates a pattern using the data determined by the line width determination unit 7.
【００２１】また、以上のような構成のパターン生成装
置を用いて、人手によりAl線幅が決定されたパターンを
検証することも可能である。その場合、線幅比較部９
が、線幅決定部７の線幅データと、人手により見積もら
れた実際の線幅データ８とを比較し、グラフィック表示
部10に、線幅決定部７のデータよりも狭い配線部分と、
反対に広い配線部分とを判別可能に画像表示するととも
に、線幅の数値を表示して設計者の検証を可能とする。Further, it is also possible to verify the pattern in which the Al line width is manually determined by using the pattern generating apparatus having the above-mentioned structure. In that case, the line width comparison unit 9
Compares the line width data of the line width determination unit 7 with the actual line width data 8 estimated manually, and displays in the graphic display unit 10 a wiring portion narrower than the data of the line width determination unit 7,
On the contrary, a wide wiring part can be displayed in an image so that it can be discriminated, and the numerical value of the line width is displayed to enable the designer to verify.
【００２２】以上のようにして、集積回路の動作経過に
おける各時間単位ごとの各セルの消費電流と各セルの端
子の接続関係とを考慮した適切なAl線幅が決定される。As described above, the appropriate Al line width is determined in consideration of the current consumption of each cell and the connection relation of the terminals of each cell in each time unit in the operation progress of the integrated circuit.
【００２３】なお、本実施例では、配線の対象としてセ
ルを取り扱ったが、配線の対象はこれに限るものではな
く、本発明のパターン生成装置はトランジスタ間の配線
の適切な線幅の決定、さらにパターン生成及びパターン
検証にも適用可能である。In this embodiment, the cell is handled as the wiring target, but the wiring target is not limited to this, and the pattern generation device of the present invention determines the appropriate line width of the wiring between the transistors. Further, it can be applied to pattern generation and pattern verification.
【００２４】また、本実施例では、決定した線幅の画像
及びその数値をグラフィック表示部に表示する場合につ
いて説明したが、プリンタ等を用いて装置外部へ出力し
てもよい。Further, in this embodiment, the case where the image of the determined line width and its numerical value are displayed on the graphic display section has been described, but it may be output to the outside of the apparatus using a printer or the like.
【００２５】さらに、本実施例では、各セルの消費電流
値としてその平均値を用いた場合について説明したが、
消費電流値はこれに限るものではない。Further, in this embodiment, the case where the average value is used as the current consumption value of each cell has been described.
The current consumption value is not limited to this.
【００２６】[0026]
【発明の効果】以上のように、本発明のパターン生成装
置は、集積回路の動作モード，動作時間ごと等の動作経
過における時間単位ごとの各回路ブロックの消費電流及
び各端子の接続関係を考慮して配線幅を自動的に決定す
るので、必要以上に太い配線によってチップサイズが大
きくなることを防ぐ一方、必要幅に満たない配線に、許
容最大電流密度を超える電流が流れて発生するエレクト
ロマイグレーションによる配線の断線を防いで集積回路
チップの信頼性を向上させるという優れた効果を奏す
る。As described above, the pattern generating apparatus of the present invention takes into consideration the operating mode of the integrated circuit, the current consumption of each circuit block for each time unit in the operation progress such as each operation time, and the connection relation of each terminal. Since the wiring width is determined automatically, the chip size is prevented from increasing due to wiring that is thicker than necessary, while electromigration that occurs when a current that exceeds the maximum allowable current density flows in wiring that does not meet the required width. This has an excellent effect of preventing the disconnection of the wiring due to and improving the reliability of the integrated circuit chip.
【図１】従来方法により決定した線幅で作成されたICチ
ップの平面図である。FIG. 1 is a plan view of an IC chip having a line width determined by a conventional method.
【図２】本発明のパターン生成装置の構成を示すブロッ
ク図である。FIG. 2 is a block diagram showing a configuration of a pattern generation device of the present invention.
【図３】本発明のパターン生成装置により作成されたIC
チップパターンの平面図である。FIG. 3 is an IC created by the pattern generation device of the present invention.
It is a top view of a chip pattern.
【図４】ICチップの各セルの実動作のタイミングを示す
タイミングチャートである。FIG. 4 is a timing chart showing the timing of actual operation of each cell of the IC chip.
１ 消費電流算出部 ２ 消費電流記憶部 ３ プロセスパラメータ格納部 ４ 必要線幅算出前処理部 ５ 位置・形状記憶部 ６ 必要線幅算出部 ７ 線幅決定部 １０ グラフィック表示部 １１ パターン生成部 １２〜１４ セル １５ VDD線 １６ GND線 １７〜１９ VDD端子 ２０〜２２ GND端子 ２３，２４ 分岐点 ２５，２６ 分岐点1 Consumption Current Calculation Section 2 Consumption Current Storage Section 3 Process Parameter Storage Section 4 Required Line Width Calculation Pre-Processing Section 5 Position / Shape Storage Section 6 Required Line Width Calculation Section 7 Line Width Determination Section 10 Graphic Display Section 11 Pattern Generation Section 12 ~ 14 cells 15 V DD line 16 GND line 17 to 19 V DD terminal 20 to 22 GND terminal 23,24 Branch point 25,26 Branch point
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成４年６月５日[Submission date] June 5, 1992
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２６[Correction target item name] 0026
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００２６】[0026]
【発明の効果】以上のように、本発明のパターン生成装
置は、集積回路の動作モード，動作時間ごと等の動作経
過における時間単位ごとの各セルの消費電流及び各端子
の接続関係を考慮して配線幅を自動的に決定するので、
必要以上に太い配線によってチップサイズが大きくなる
ことを防ぐ一方、必要幅に満たない配線に、許容最大電
流密度を超える電流が流れて発生するエレクトロマイグ
レーションによる配線の断線を防いで集積回路チップの
信頼性を向上させるという優れた効果を奏する。As described above, the pattern generating apparatus of the present invention takes into consideration the operating mode of the integrated circuit, the current consumption of each cell for each time unit in the operation progress such as each operation time, and the connection relation of each terminal. Since the wiring width is automatically determined by
While preventing the chip size from increasing due to wiring that is thicker than necessary, it prevents the wiring from breaking due to electromigration that occurs when a current that exceeds the maximum allowable current density flows in the wiring that is less than the required width, and the reliability of the integrated circuit chip is improved. It has an excellent effect of improving the property.
Claims (1)
路ブロックの各端子が結線される集積回路のパターンを
生成する装置において、集積回路を構成する各回路ブロ
ックの消費電流を、該集積回路の動作経過の所定時間単
位ごとに算出する消費電流算出部と、算出された消費電
流値から各々の電源端子及びグランド端子毎に流れる電
流値を記憶保持する消費電流記憶部と、消費電流算出部
が算出した消費電流から求まる各回路ブロックの各端子
を流れる電流値と配線に用いる導体の電気的特性に関わ
るデータとに基づいて各端子に必要な配線幅を算出する
端子配線幅算出部と、前記消費電流算出部による算出デ
ータと前記端子配線幅算出部による算出データと電流の
流れにおける各端子の位置関係のデータとに基づいて、
端子の結線関係及び前記所定時間単位ごとの各回路ブロ
ックの消費電流に即した配線の必要線幅を算出する必要
線幅算出部と、必要線幅算出部が算出した必要線幅を前
記導体の加工可能な最小線幅以上の値に補正して配線幅
を決定する線幅決定部と、線幅決定部により決定された
配線幅に基づくデータを装置外部へ出力する手段と、線
幅決定部により決定された配線幅でパターンを生成する
パターン生成部とを備えたことを特徴とするパターン生
成装置。1. In an apparatus for generating a pattern of an integrated circuit in which terminals of a plurality of circuit blocks are connected by wirings branched into a plurality of stages, the current consumption of each circuit block forming the integrated circuit is calculated as follows. A current consumption calculation unit that calculates each predetermined time unit of operation progress, a current consumption storage unit that stores and holds the current value that flows for each power supply terminal and ground terminal from the calculated current consumption value, and the current consumption calculation unit. A terminal wiring width calculation unit that calculates a wiring width required for each terminal based on a current value flowing through each terminal of each circuit block obtained from the calculated consumption current and data relating to electrical characteristics of a conductor used for wiring; Based on the calculation data by the consumption current calculation unit, the calculation data by the terminal wiring width calculation unit, and the data of the positional relationship of each terminal in the current flow,
A necessary line width calculation unit for calculating the necessary line width of the wiring according to the terminal connection relation and the current consumption of each circuit block for each of the predetermined time units, and the necessary line width calculated by the necessary line width calculation unit for the conductor. A line width determining unit that determines the wiring width by correcting it to a value equal to or greater than the minimum processable line width, a unit that outputs data based on the wiring width determined by the line width determining unit to the outside of the device, and a line width determining unit. And a pattern generation unit that generates a pattern with the wiring width determined by the pattern generation device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4014767A JP2826686B2 (en) | 1992-01-30 | 1992-01-30 | Pattern generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4014767A JP2826686B2 (en) | 1992-01-30 | 1992-01-30 | Pattern generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05206276A true JPH05206276A (en) | 1993-08-13 |
| JP2826686B2 JP2826686B2 (en) | 1998-11-18 |
Family
ID=11870226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4014767A Expired - Fee Related JP2826686B2 (en) | 1992-01-30 | 1992-01-30 | Pattern generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2826686B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5737580A (en) * | 1995-04-28 | 1998-04-07 | International Business Machines Corporation | Wiring design tool improvement for avoiding electromigration by determining optimal wire widths |
| JP2003058595A (en) * | 2001-08-16 | 2003-02-28 | Mitsubishi Electric Corp | Device for analyzing circuit |
| JP2006287198A (en) * | 2005-03-08 | 2006-10-19 | Sanyo Epson Imaging Devices Corp | Semiconductor circuit, circuit of driving electrooptical device, and electronic apparatus |
| CN100338760C (en) * | 2004-06-01 | 2007-09-19 | 恩益禧电子股份有限公司 | Semiconductor integrated circuit, method for designing semiconductor integrated circuit and system for designing semiconductor integrated circuit |
| US7847759B2 (en) | 2005-03-08 | 2010-12-07 | Epson Imaging Devices Corporation | Semiconductor circuit, driving circuit of electro-optical device, and electronic apparatus |
| CN103235849A (en) * | 2013-04-18 | 2013-08-07 | 清华大学 | Current-drive integrated circuit automatic wiring method and device |
| JP2017139361A (en) * | 2016-02-04 | 2017-08-10 | 日立オートモティブシステムズ株式会社 | Semiconductor device and load drive device |
| US9886537B2 (en) | 2014-03-31 | 2018-02-06 | Socionext Inc. | Method of supporting design, computer product, and semiconductor integrated circuit |
-
1992
- 1992-01-30 JP JP4014767A patent/JP2826686B2/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5737580A (en) * | 1995-04-28 | 1998-04-07 | International Business Machines Corporation | Wiring design tool improvement for avoiding electromigration by determining optimal wire widths |
| JP4548985B2 (en) * | 2001-08-16 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | Circuit analyzer |
| JP2003058595A (en) * | 2001-08-16 | 2003-02-28 | Mitsubishi Electric Corp | Device for analyzing circuit |
| CN100338760C (en) * | 2004-06-01 | 2007-09-19 | 恩益禧电子股份有限公司 | Semiconductor integrated circuit, method for designing semiconductor integrated circuit and system for designing semiconductor integrated circuit |
| JP2011227522A (en) * | 2005-03-08 | 2011-11-10 | Epson Imaging Devices Corp | Electro-optical device and electronic equipment |
| US7847759B2 (en) | 2005-03-08 | 2010-12-07 | Epson Imaging Devices Corporation | Semiconductor circuit, driving circuit of electro-optical device, and electronic apparatus |
| JP2006287198A (en) * | 2005-03-08 | 2006-10-19 | Sanyo Epson Imaging Devices Corp | Semiconductor circuit, circuit of driving electrooptical device, and electronic apparatus |
| US8537152B2 (en) | 2005-03-08 | 2013-09-17 | Epson Imaging Devices Corporation | Semiconductor circuit, driving circuit of electro-optical device, and electronic apparatus |
| US8552935B2 (en) | 2005-03-08 | 2013-10-08 | Epson Imaging Devices Corporation | Semiconductor circuit, driving circuit of electro-optical device, and electronic apparatus |
| JP2013214071A (en) * | 2005-03-08 | 2013-10-17 | Epson Imaging Devices Corp | Electro-optical device and electronic apparatus |
| US9262985B2 (en) | 2005-03-08 | 2016-02-16 | Epson Imaging Devices Corporation | Semiconductor circuit, driving circuit of electro-optical device, and electronic apparatus |
| CN103235849A (en) * | 2013-04-18 | 2013-08-07 | 清华大学 | Current-drive integrated circuit automatic wiring method and device |
| CN103235849B (en) * | 2013-04-18 | 2016-01-20 | 清华大学 | The integrated circuit automatic wiring method that electric current drives and device |
| US9886537B2 (en) | 2014-03-31 | 2018-02-06 | Socionext Inc. | Method of supporting design, computer product, and semiconductor integrated circuit |
| JP2017139361A (en) * | 2016-02-04 | 2017-08-10 | 日立オートモティブシステムズ株式会社 | Semiconductor device and load drive device |
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| Publication number | Publication date |
|---|---|
| JP2826686B2 (en) | 1998-11-18 |
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