JP3006140B2 - Automatic wiring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic wiring system for an integrated circuit or a printed circuit board.

[0002]

2. Description of the Related Art In a conventional automatic wiring method, a wiring area is treated as a grid, all the grids are secured in a storage area, and labels are assigned to each grid based on wavefront propagation from a grid corresponding to a terminal to be wired. Then, when the wavefront reaches the target terminal, there is a "maze method" in which the label is traced in reverse to complete the path, and the wiring area is shared by the processors constituting the parallel computer and the wavefront propagation is performed in parallel. The scheme is well known. This prior art is described in 1986.
It is detailed in IPSJ Transactions on Parallel Routing Processor Prototype Research.

[0003]

An object of the method in which the "maze method" is parallelized is to speed up the wiring processing of one set of pin pairs in parallel. However, since the degree of parallelism inherent in the wiring processing of one set of pin pairs is not so high, the effect of increasing the speed by the parallel processing cannot be obtained so much.

[0004]

According to the present invention, a schematic wiring path indicating where a wiring path of a pin pair to be routed in a wiring area should pass during automatic wiring processing of an integrated circuit or a printed circuit board. Decide. Next, pin pairs whose schematic wiring paths are independent from each other are assigned to different computers, and each computer realizes parallel processing by performing detailed wiring of the assigned pin pairs in the schematic wiring paths.

[0005]

According to the present invention, in the automatic wiring processing of an integrated circuit or a printed circuit board, a schematic wiring path indicating where in the wiring area the wiring path of the pin pair to be wired should be determined. By assigning pin pairs whose paths are mutually independent to different computers, and by performing detailed wiring of the assigned pin pairs in the schematic wiring path, each computer achieves high parallelism and speeds up wiring processing.

[0006]

FIG. 1 is a plan view showing a state of a wiring region 1 before wiring. The example shown here shows some terminals 1
This is for wiring the net constituted by 1. FIG.
FIG. 5 is a plan view showing a state of a wiring area where schematic wiring has been completed. In the wiring area of this drawing, a schematic wiring path 3 is generated so as to include a plurality of terminals constituting a net. FIG. 3 is a diagram showing that the independent schematic wiring paths 3 are assigned to the computers A, B, C and D. Since the two general wiring paths 3 assigned to the computer D are not independent, they are not divided into separate computers. Since the general wiring path 3 assigned to each computer does not intersect with the general wiring path 3 assigned to another computer, no detailed communication between the computers is required for detailed wiring in the general wiring path 3.
FIG. 4 shows that the computer A, the computer B, the computer C, and the computer D
Detailed wiring 4 of pin pairs in each general wiring area in charge
Is shown.

[0007]

According to the present invention, during automatic wiring processing of an integrated circuit or a printed circuit board, a schematic wiring path indicating which part of a wiring path of a pin pair to be wired should pass through in a wiring area is determined. By assigning pin pairs whose schematic wiring paths are independent from each other to different computers, and by performing detailed wiring of the pin pairs assigned to each computer within the schematic wiring paths, high parallelism is obtained and wiring processing is accelerated. There is an effect of doing.

[Brief description of the drawings]

FIG. 1 is a diagram showing a state of a wiring area before wiring.

FIG. 2 is a diagram showing a state in which schematic wiring is completed.

FIG. 3 is a diagram illustrating a state where a schematic wiring area is allocated to a plurality of computers.

FIG. 4 is a diagram showing a state where each computer has finished detailed wiring of a pin pair in a schematic wiring area.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wiring area 2 Obstacle 3 Schematic wiring route 4 Detailed wiring 11 Terminal A, B, C, D Computer

Claims (1)

(57) [Claims] At the time of automatic wiring processing of an integrated circuit or a printed circuit board, first, a rough wiring path indicating a rough wiring path is obtained, and then a plurality of pin pairs or nets whose rough wiring paths are independent from each other are connected to a plurality of nets. Automatic wiring method characterized by detailed wiring in parallel with a computer.