JPS6290574A - Voltage detection circuit - Google Patents

Voltage detection circuit

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Publication number
JPS6290574A
JPS6290574A JP27011584A JP27011584A JPS6290574A JP S6290574 A JPS6290574 A JP S6290574A JP 27011584 A JP27011584 A JP 27011584A JP 27011584 A JP27011584 A JP 27011584A JP S6290574 A JPS6290574 A JP S6290574A
Authority
JP
Japan
Prior art keywords
transistor
emitter
collector
voltage
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27011584A
Other languages
Japanese (ja)
Inventor
Kenji Kano
賢次 加納
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP27011584A priority Critical patent/JPS6290574A/en
Publication of JPS6290574A publication Critical patent/JPS6290574A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To detect a voltage with good accuracy by eliminating the effect of temp. and power source voltage on input threshold voltage, by adjusting the values of first and second resistors connected to the first transistor TR, which is connected to the input terminal of a voltage detection circuit, and connected to the second transistor TR connected between said first transistor TR and the earth. CONSTITUTION:A first transistor TR1 is connected to the output point 43 of the current mirror circuit 30 connected to the power source 50 of a voltage detection circuit and an input terminal 41 is connected to the base of the first transistor TR1. The collector of a second transistor TR2 is connected to the emitter of the first transistor TR1 through a first resistor 11 and the emitter of the second transistor TR2 is connected to earth through a second resistor 12. Further, a third transistor TR3 is connected to the base of the second transistor TR2 and the common connection point of the base and collector of the third transistor TR3 is connected to the output point 44 of the circuit 30 and the emitter thereof is earthed. A fourth transistor TR4 of which the collector is connected to the output terminal 42 is connected to the collector of the transistor TR2 and the emitter thereof is earthed. Then, the values of the resistors 11, 12 are controlled to remove the effect of the variation of temp. and the power source 50.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は入力電圧がいき値を超えたか否かを検出する回
路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for detecting whether an input voltage exceeds a threshold value.

〔従来の技術〕[Conventional technology]

従来の電圧検出回路を第2図に示す。第2図において、
20は基準電圧を発生する基準電圧発生回路、21は基
準電圧と入力端子を比較する比較器、41は被測定電圧
が入力される入力端子、42は比較器21からの出力電
圧が出力される出力端子である。
A conventional voltage detection circuit is shown in FIG. In Figure 2,
20 is a reference voltage generation circuit that generates a reference voltage; 21 is a comparator that compares the reference voltage with an input terminal; 41 is an input terminal to which a voltage to be measured is input; and 42 is an output voltage from the comparator 21. It is an output terminal.

このように構成された回路の動作について説明する。基
準電圧発生回路は温度、電源電圧に依存しない電圧を発
生する。この発生した電圧を比較器21の子端子に人力
し、被測定電圧を比較器21の一端子に入力しすること
により、被測定電圧を検出する。比較器21は比較電圧
を出力端子42に出力する。
The operation of the circuit configured in this way will be explained. The reference voltage generation circuit generates a voltage that is independent of temperature and power supply voltage. By inputting this generated voltage to a child terminal of the comparator 21 and inputting the voltage to be measured to one terminal of the comparator 21, the voltage to be measured is detected. Comparator 21 outputs a comparison voltage to output terminal 42 .

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしこのような回路においては、基準電圧の発生機能
と電圧の比較機能とが別個の回路ブロックで行なわれる
ため、多くの素子を必要とするという問題がある。
However, in such a circuit, the function of generating the reference voltage and the function of comparing the voltages are performed in separate circuit blocks, so there is a problem that a large number of elements are required.

本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、基準電圧発生と電圧比較の機能
が一体化され、温度、電源電圧に動作が無関係であり、
また回路構成が簡単な電圧検出回路を提供することにあ
る。
The present invention has been made in view of these points, and its purpose is to integrate the functions of reference voltage generation and voltage comparison, and whose operation is independent of temperature and power supply voltage.
Another object of the present invention is to provide a voltage detection circuit with a simple circuit configuration.

〔問題点を解決するための手段〕[Means for solving problems]

このような目的を達成するために本発明は、ベースが入
力端子に接続された第1のトランジスタと、コレクタが
抵抗器を介して第1のトランジスタのエミッタにエミッ
タが抵抗器を介してアースに接続された第2のトランジ
スタと、コレクタとベースが第2のトランジスタのベー
スにエミッタがアースに接続された第3のトランジスタ
と、コレクタが出力端子にエミッタがアースにベースが
第2のトランジスタのコレクタに接続された第4のトラ
ンジスタと、入力点が第1のトランジスタのコレクタに
出力点が前記第3のトランジスタのコレクタに接続され
たカレントミラー回路とを設けるようにしたものである
To achieve this purpose, the present invention includes a first transistor whose base is connected to an input terminal, whose collector is connected to the emitter of the first transistor through a resistor, and whose emitter is connected to ground through a resistor. a third transistor whose collector and base are connected to the base of the second transistor and whose emitter is connected to ground; and whose collector and base are connected to the base of the second transistor and whose emitter is connected to ground and whose base is connected to the collector of the second transistor. and a current mirror circuit whose input point is connected to the collector of the first transistor and whose output point is connected to the collector of the third transistor.

〔作用〕[Effect]

本発明においては、第1のトランジスタのエミッタと第
2のトランジスタのコレクタとの間の第1の抵抗器、第
2のトランジスタのエミッタとアースとの間の第2の抵
抗器などの値を適当に選べば、入力のいき値電圧の温度
依存性はなくなる。
In the present invention, the values of the first resistor between the emitter of the first transistor and the collector of the second transistor, the second resistor between the emitter of the second transistor and ground, etc. are set appropriately. If selected, the temperature dependence of the input threshold voltage will disappear.

〔実施例〕〔Example〕

本発明に係わる電圧検出回路の一実施例を第1図に示す
。第1図において、Iばベースが入力端子41に接続さ
れた第1のトランジスタ、2はコレクタが第1の抵抗器
11を介してトランジスタ1のエミッタにエミッタが第
2の抵抗器12を介してアースに接続された第2のトラ
ンジスタ、3はコレクタとベースがトランジスタ2のベ
ースにエミッタがアースに接続された第3のトランジス
タ、4はコレクタが出力端子42にエミッタがアースに
ベースがトランジスタ2のコレクタに接続された第4の
トランジスタ、30は入力電流に比例した出力電流を出
力するカレントミラー回路、30a、30bはカレント
ミラー回路30を構成するトランジスタ、43はカレン
トミラー回路30に電流が人力されるための入力点、4
4はカレントミラー回路30から電流が出力されるため
の出力点、50は本回路を動作させるための電源である
An embodiment of a voltage detection circuit according to the present invention is shown in FIG. In FIG. 1, I is a first transistor whose base is connected to an input terminal 41, and 2 is a transistor whose collector is connected to the emitter of transistor 1 through a first resistor 11 and whose emitter is connected through a second resistor 12. 3 is a third transistor whose collector and base are connected to the base of transistor 2 and whose emitter is connected to earth; 4 is a third transistor whose collector and base are connected to the base of transistor 2 and whose emitter is connected to earth; and 4 is a transistor whose collector and base are connected to the base of transistor 2 and whose emitter is connected to earth; A fourth transistor connected to the collector; 30 is a current mirror circuit that outputs an output current proportional to the input current; 30a and 30b are transistors forming the current mirror circuit 30; 43 is a current mirror circuit that outputs an output current proportional to the input current; Input point for input, 4
4 is an output point for outputting current from the current mirror circuit 30, and 50 is a power source for operating this circuit.

次にこのように構成された本実施例の動作について説明
する。入力端子41における入力電圧が低いとき、トラ
ンジスタ1のエミッタ電位は低い電位にあるので、1−
ランジスタ2のコレクタ電位も低く、トランジスタ4は
オフ状態にある。逆に入力端子41における入力電圧が
高いとき、トランジスタ1のエミッタ電位は高い電位に
あるので、トランジスタ2のコレクタ電位も高く、トラ
ンジスタ4はオン状態にある。
Next, the operation of this embodiment configured as described above will be explained. When the input voltage at input terminal 41 is low, the emitter potential of transistor 1 is at a low potential, so 1-
The collector potential of transistor 2 is also low, and transistor 4 is in an off state. Conversely, when the input voltage at input terminal 41 is high, the emitter potential of transistor 1 is at a high potential, so the collector potential of transistor 2 is also high, and transistor 4 is in an on state.

次にトランジスタ4がオフ状態からオン状態に移るため
の入力のいき値電圧について説明する。
Next, the input threshold voltage at which the transistor 4 changes from the off state to the on state will be explained.

このいき値においては、トランジスタ1.2,3.4は
活性領域にあり、hFEが十分高いものとすれば、その
ベース電流は無視できるので、以下の説明においてはベ
ース電流はないものとみなす。
At this threshold, transistors 1.2, 3.4 are in the active region and their base currents can be ignored provided hFE is high enough, so in the following description it is assumed that there is no base current.

カレントミラー回路30は、その入力電流に対してm倍
の電流を出力電流として発生するとすれば、トランジス
タ1のコレクタ電流ICIとトランジスタ3のコレクタ
電流rc3との間には次式(1)の関係が成立する。
Assuming that the current mirror circuit 30 generates a current m times as much as its input current as an output current, the relationship between the collector current ICI of the transistor 1 and the collector current rc3 of the transistor 3 is expressed by the following equation (1). holds true.

IC3=m・ic+  ・・・・ (1)トランジスタ
2のエミッタ面積がトランジスタ3のエミッタ面積のn
倍であり+RZを抵抗器12の抵抗値、kをポルツマン
定数、Tを絶対温度。
IC3=m・ic+ (1) The emitter area of transistor 2 is n of the emitter area of transistor 3
+RZ is the resistance value of resistor 12, k is Portzmann's constant, and T is the absolute temperature.

qを電子電荷とすると、トランジスタ2のエミッタ電流
1ttとトランジスタ3のエミッタ電流IE3との間に
は、ショックレーの方程式より、次式(2)の関係が成
立する。
When q is an electronic charge, the following equation (2) holds between the emitter current 1tt of the transistor 2 and the emitter current IE3 of the transistor 3 based on Shockley's equation.

Rt−IEZ= (kT/q) 7!n (n IE3
/IEz)・・・・ (2) 本実施例においては、ベース電流はないものとみなして
いるので、トランジスタ1のコレクタ電流はトランジス
タ1のエミッタ電流、トランジスタ2のコレクタ電流、
トランジスタ2のエミッタ電流と等しい。またトランジ
スタ3のコレクタ電流はトランジスタ3のエミッタ電流
と等しい。したかって、次式(3)が成立する。
Rt-IEZ= (kT/q) 7! n (n IE3
/IEz)... (2) In this example, it is assumed that there is no base current, so the collector current of transistor 1 is the emitter current of transistor 1, the collector current of transistor 2,
Equal to the emitter current of transistor 2. Further, the collector current of transistor 3 is equal to the emitter current of transistor 3. Therefore, the following equation (3) holds true.

Rz・Icz= (kT/ q)12 n (m−n)
・・・・ (3) したがって、抵抗器11での電圧降下Vll+は、抵抗
器11の抵抗値をR1とすると、次式(4〕で求められ
る。
Rz・Icz= (kT/q)12 n (m-n)
(3) Therefore, the voltage drop Vll+ across the resistor 11 is determined by the following equation (4), assuming that the resistance value of the resistor 11 is R1.

V +z = R+ ’ I t□ −(R+/RzL(kT/ q)l n (m−n)・
・・・ (4) この(4)式から入力のいき値電圧VINTHは、トラ
ンジスタ1のベース・エミッタ間電圧をvgt+、トラ
ンジスタ4のベース・エミッタ間電圧をV B E 4
とすると、次式(5)のようになる。
V +z = R+ ' I t□ -(R+/RzL(kT/q)l n (m-n)・
... (4) From this equation (4), the input threshold voltage VINTH is the voltage between the base and emitter of transistor 1 as vgt+, and the voltage between the base and emitter of transistor 4 as V B E 4
Then, the following equation (5) is obtained.

VINTH=VREl +VB!。VINTH=VREl +VB! .

+ (R+/Rz)・(kT/ q)1 n (m −
n)・・・・ (5) VBEI+  VBE4は負の温度係数をもち、はぼ次
式(6)のように表わされる。
+ (R+/Rz)・(kT/q)1 n (m −
n)... (5) VBEI+VBE4 has a negative temperature coefficient, and is expressed as the following equation (6).

Vlltt +v!14” 2  (Vgo−αIT−
α4T)・ ・ ・ ・ (6) ■9゜−1,25であるので、式(5)は次式(7)の
ようになる。
Vlltt +v! 14” 2 (Vgo-αIT-
α4T)・・・・・(6) ■Since 9°-1,25, equation (5) becomes the following equation (7).

■1.4□n=2.5V  (α、+αa) T+ (
R+/Rz)・(kT/q)in  (m−n)・・・
・ (7) したがって α、+αa= (R+/ Rz)・(k/ (1)  
i n (m−n)となるようにR,、R,、m、nを
設定すれば、入力のいき値電圧は温度依存性のない、約
2.5vのいき値電圧となる。また式(7)は電源電圧
の関数ともなっていないので、電源電圧依存性もない。
■1.4□n=2.5V (α, +αa) T+ (
R+/Rz)・(kT/q)in (m-n)...
・ (7) Therefore α, +αa= (R+/Rz)・(k/ (1)
If R, , R, , m, and n are set so that i n (m−n), the input threshold voltage becomes a temperature-independent threshold voltage of about 2.5 V. Furthermore, since equation (7) is not a function of the power supply voltage, there is no dependence on the power supply voltage.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、第1の抵抗器を第1のト
ランジスタのエミッタと第2のトランジスタのコレクタ
との間、第2の抵抗器を第2のトランジスタのエミッタ
とアースとの間に設け、これらの抵抗器の値を調整する
ようにしたので、入力のいき値電圧に対する温度および
電源電圧の影響をなくし電圧を精度よく検出できる効果
がある。
As explained above, in the present invention, the first resistor is placed between the emitter of the first transistor and the collector of the second transistor, and the second resistor is placed between the emitter of the second transistor and the ground. Since the values of these resistors are adjusted, the effects of temperature and power supply voltage on the input threshold voltage can be eliminated, and the voltage can be detected with high accuracy.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係わる電圧検出回路の一実施例を示す
回路図、第2図は従来の電圧検出回路を示すブロック系
統図である。 1.2,3,4,30a、30b・−)ランジスタ、1
1.12・・・・抵抗器、30・・・・カレントミラー
回路、41・・・・入力端子、42・・・・出力端子、
43・・・・入力点、44・・・・出力点、50・・・
・電源。
FIG. 1 is a circuit diagram showing an embodiment of a voltage detection circuit according to the present invention, and FIG. 2 is a block system diagram showing a conventional voltage detection circuit. 1.2,3,4,30a,30b・-) transistor, 1
1.12...Resistor, 30...Current mirror circuit, 41...Input terminal, 42...Output terminal,
43...Input point, 44...Output point, 50...
·power supply.

Claims (1)

【特許請求の範囲】[Claims] ベースが入力端子に接続された第1のトランジスタと、
コレクタが第1の抵抗器を介して前記第1のトランジス
タのエミッタにエミッタが第2の抵抗器を介してアース
に接続された第2のトランジスタと、コレクタとベース
が前記第2のトランジスタのベースにエミッタがアース
に接続された第3のトランジスタと、コレクタが出力端
子にエミッタがアースにベースが前記第2のトランジス
タのコレクタに接続された第4のトランジスタと、入力
点が前記第1のトランジスタのコレクタに出力点が前記
第3のトランジスタのコレクタに接続されたカレントミ
ラー回路とを備えたことを特徴とする電圧検出回路。
a first transistor whose base is connected to the input terminal;
a second transistor whose collector is connected to the emitter of the first transistor through a first resistor and whose emitter is connected to ground through a second resistor; and whose collector and base are connected to the base of the second transistor. a third transistor whose emitter is connected to ground, a fourth transistor whose collector is connected to the output terminal, whose emitter is connected to ground and whose base is connected to the collector of the second transistor, and whose input point is the first transistor. and a current mirror circuit whose output point is connected to the collector of the third transistor.
JP27011584A 1984-12-19 1984-12-19 Voltage detection circuit Pending JPS6290574A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27011584A JPS6290574A (en) 1984-12-19 1984-12-19 Voltage detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27011584A JPS6290574A (en) 1984-12-19 1984-12-19 Voltage detection circuit

Publications (1)

Publication Number Publication Date
JPS6290574A true JPS6290574A (en) 1987-04-25

Family

ID=17481748

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27011584A Pending JPS6290574A (en) 1984-12-19 1984-12-19 Voltage detection circuit

Country Status (1)

Country Link
JP (1) JPS6290574A (en)

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