JPS6289342A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the operating speed of a whole master slice type semiconductor integrated circuit without augmenting the area of the chip by a method wherein the MOS Trs of parts in the circuit are each provided with contacts for reducing a parasitic resistance plural pieces. CONSTITUTION:A source region 12 and a drain region 13 are each provided with contacts 221 and 222 and contacts 231 and 232 two pieces by two pieces and the respective fellow contacts are connected with first layer wirings 15, tunnel wirings 16 which are layers different from the wirings 15 and through holes 321 and 322, or 331 and 332. At this time, the resistance components of the wirings 15 and 16 are sufficiently smaller compared to those of the wirings 15 and 16 are sufficiently smaller compared to those of the source and drain regions and can be ignored. By this way, in case the overall resistivity between lead-out wirings S-D from each one contact of the source and drain regions is calculated, the resistance component between the S-D becomes smaller. A parasitic resistance component can be reduced in order further increasing the number of contact and by connecting those fellow contacts with wirings.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an MO8 field effect transistor (hereinafter referred to as MO8 field effect transistor).
Regarding semiconductor integrated circuits having Tr ), especially MOS
The present invention relates to a semiconductor integrated circuit in which the parasitic resistance of the source region and drain region of T r is reduced.

[Conventional technology]

A master slice type integrated circuit, particularly a type of integrated circuit called a gate array, has an underlying structure in which many elements of the same shape are arranged in an array on a semiconductor substrate, and by changing the wiring pattern on the upper layer, a desired pattern can be achieved. Many integrated circuits with logic functions can be derived.

The shapes, electrical characteristics, etc. of the elements pre-arranged on the substrate have been significantly standardized in order to correspond to any circuit configuration for achieving a desired logical function. A dedicated wiring area is also provided to support automatic design.

FIG. 2 shows an example of the planar structure of Mos'rr arranged in a conventional MO8 type gate array. Abstract Mefuichi MO
The 8Tr is surrounded by an insulating region 10 from other elements, a gate electrode 11 passes through the center, a channel is formed directly below it depending on the gate potential, and current flows between the source region 12 and drain region 13. . The source and drain regions have the same conditions for device formation and are completely compatible in terms of circuit connection. These gate electrodes, source regions, and drain regions are connected to other elements or power supply wiring by contacts 14, first layer wiring 15, etc. as necessary. Furthermore, the upper layer of this MOS TR region is also used as a free wiring area so that other wirings 151, 152, etc. can pass through, and there is a wiring free track group 300 for the first layer wiring, and furthermore, In general, in gate arrays in which free track groups 400 in the wiring area for the upper second layer wiring are provided vertically and horizontally, the required number of elements and the wiring tracks required for the wiring area depend on the integration scale (-number of mounted gates). The number is almost decided. Therefore, in order to reduce the chip area and further reduce the parasitic capacitance that hinders high-speed operation of the circuit, it is important to reduce the area occupied by each element and the wiring width (pitch).

Current gain 1 required for each MOS '1' r
m is proportional to the ratio W/L of gate length and gate width W.

When attempting to reduce the MO8Tr area while maintaining the required 2 m on the circuit, there is a limit to the reduction in gate length due to problems such as gate electrode patterning technology, and a certain gate width W is inevitably required.

The MO8Tr actually used is L: 1μ.
Front and back, W: There are some tens of microns, and the overall shape of the MOS transistor tends to be elongated along the W direction of the gate electrode. Further, the contact shapes of the source region and drain region at this time are reduced to the minimum size that can be formed in the manufacturing process in order to pass more wires within a certain wiring region.

FIG. 3 schematically shows the parasitic resistance of the source and drain regions of the MOS transistor, which has an elongated shape along the width direction of the gate electrode. Area contacts 22.
It has been reduced to the same size as 23. Contacts for the source and drain regions are provided approximately at the center of each region, and the lead wiring (first layer wiring) from each contact is indicated by 01 for the gate, 81 for the source, and D for the drain. Further, the parasitic resistances of the source and drain regions are indicated by R81 to R84 and D1 to R, D4, respectively.

Figure 4 shows MOSTr in Figure 3 divided into small sections 501 to 5.
05, and the equivalent circuit is shown as a set of small sections MO8Tr of Tll01 to 'I'*os, including parasitic resistance. As is clear from FIG. 4, the series resistance from the contacts in the small sections MOSTr located far from the contacts 22 and 23 in the source and drain regions is large; It may extend to several hundred ohms.

[Problem that the invention seeks to solve]

As mentioned above, in conventional semiconductor integrated circuits, MO8Tr
has an elongated shape along the width direction of the gate electrode, and the contact positions of the source region and drain region are located at the center of each region, so the source and drain regions away from the contact position are The parasitic resistance in the region increases, effectively reducing the MO8Tr's resistance.
There is a drawback that the door is greatly reduced, and the load driving ability and operating speed of the circuit using this MO8Tr are reduced.

[Means for solving problems]

The semiconductor integrated circuit of the present invention is a master slice type semiconductor integrated circuit including M 08 T r, in which at least one M 08 T r has a source region or a drain region having a plurality of contacts, and the plurality of contacts It has a structure in which contacts are directly connected by a metallized pattern, and this MO8Tr is provided in the internal region of the chip.

〔Example〕

Examples of the present invention will be described below.

FIG. 1 is a plan view of one embodiment of the present invention. Parts equivalent to those in Figure 3 are indicated with the same symbols.

In FIG.
, 232 are provided, and between each contact there is a first layer wiring 15, a tunnel wiring 16 in a different layer, and through holes 321, 322 or 331, 3.
It is connected with 32. In this case, the resistance of the wirings 15 and 16 is sufficiently small compared to the resistance of the source and drain regions and can be ignored. FIG. 5 shows an equivalent circuit of FIG. 1, similar to FIG. 4 for FIG. 3. Comparing FIG. 4 and FIG. 5, we see that the parasitic resistances R8I to R84 in the source and drain regions.

Assuming that the resistance values of RDt to RD4 are the same value R, each subdivision MOS Tr T,. , ~'1465 is ON (conducting), the parasitic resistance of the MO8Tr (channel region) itself is calculated as rt, and the total resistance value between the lead wires S and D from each contact in the source and drain regions is calculated as follows. The figure shows r(4R2+6R-rt+r”)/(4
R''+101 (-rt +5 r%) Figure 5 shows r (
2B"+3R-rt+rt)/(4R"+101
%-rt+5 r2t), and the one in Figure 5 is S-D.
It can be seen that the resistance between them is small. Furthermore, by increasing the number of contacts and connecting them with wiring, it is possible to gradually reduce the parasitic resistance. However, if the MO8Tr of the entire chip is structured as in the embodiment shown in Figure 1, each time the number of contacts in the source and drain regions is increased, free tracks in the wiring area of each layer will be used up, so the wiring area will be expanded. Therefore, the chip area must be increased. However, in practice, by implementing the present invention only in the Mos'rr that constitutes the part that determines the operating speed of the entire integrated circuit, the integrated circuit can be integrated without using much of the wiring area within the chip or increasing the chip area. The overall operating speed can be improved.

Particularly in the case of gate arrays, during the automatic design process using a computer, it is easy to identify key points in terms of operating speed within the integrated circuit, making it possible to effectively implement unexploited areas with less man-hours. A significant improvement in circuit performance can be expected.

〔Effect of the invention〕

As explained above, the present invention provides a plurality of contacts for reducing parasitic resistance in some MO8Trs in a master slice type semiconductor integrated circuit, thereby improving the overall operation of the integrated circuit without increasing the chip area. This has the effect of easily realizing speed improvement.

[Brief explanation of drawings]

FIG. 1 is a plan view of a MO8Tr used in an embodiment of the present invention; FIG. 2 is a plan view of a general MO8Tr in a conventional master slice type semiconductor integrated circuit; FIG. 3 is a plan view of an MO8Tr used in an embodiment of the present invention;
MO8Tr Hiranai diagram showing the parasitic resistance associated with 'l''r, the equivalent circuit of FIGS. 4 and 3, the equivalent circuit of FIG. 5, and the equivalent circuit of FIG. 1. 11...Gate electrode, 12. ...Source region, 13...Drain region, 15...
・First layer wiring, 16...Tunnel wiring, RDI
~RD4...Drain region parasitic resistance, R8I~
884...Source region parasitic resistance. 4〃

Claims (3)

[Claims] (1) A master slice type semiconductor integrated circuit including a field effect transistor, wherein a source region or a drain region of at least one field effect transistor has a plurality of contacts. (2) The semiconductor integrated circuit according to claim (1), wherein a plurality of contacts of the source region or the drain region are directly connected. (3) Claim No. 3, characterized in that the field effect transistor is provided in an internal region of a chip.
1) The semiconductor integrated circuit described in item 1).