JPS6289038U - - Google Patents

Info

Publication number
JPS6289038U
JPS6289038U JP17904785U JP17904785U JPS6289038U JP S6289038 U JPS6289038 U JP S6289038U JP 17904785 U JP17904785 U JP 17904785U JP 17904785 U JP17904785 U JP 17904785U JP S6289038 U JPS6289038 U JP S6289038U
Authority
JP
Japan
Prior art keywords
microprogram
storage
match
stores
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17904785U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17904785U priority Critical patent/JPS6289038U/ja
Publication of JPS6289038U publication Critical patent/JPS6289038U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図、
第2図は第1図の動作中、クロツク位相合わせの
手順を示すフローチヤート、第3図は第2図の説
明に必要なタイミングチヤートである。 1…ストレージ、2…アドレスレジスタ、3…
インクリメンタ、4…切換器、5…クロツクジエ
ネレータ、6…分周器、7…マルチプレクサ、1
1…バス。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a flowchart showing the procedure of clock phase adjustment during the operation of FIG. 1, and FIG. 3 is a timing chart necessary for explaining FIG. 2. 1...Storage, 2...Address register, 3...
Incrementer, 4... Switch, 5... Clock generator, 6... Frequency divider, 7... Multiplexer, 1
1...Bus.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マイクロプログラムのアドレスを発生するアド
レス発生部と、マイクロプログラムを記憶してお
くストレージと、ストレージ出力により制御され
、複数の異なるクロツク周波数で動作する論理ブ
ロツクからなるマイクロプログラム方式において
、各論理ブロツクの周波数に合うように基本クロ
ツクの分周回路を設けることを特徴としたマイク
ロプログラム処理装置。
In the microprogram system, which consists of an address generator that generates microprogram addresses, a storage that stores the microprogram, and logic blocks that are controlled by storage output and operate at multiple different clock frequencies, the frequency of each logic block is A microprogram processing device characterized by being provided with a basic clock frequency dividing circuit to match the current.
JP17904785U 1985-11-22 1985-11-22 Pending JPS6289038U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17904785U JPS6289038U (en) 1985-11-22 1985-11-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17904785U JPS6289038U (en) 1985-11-22 1985-11-22

Publications (1)

Publication Number Publication Date
JPS6289038U true JPS6289038U (en) 1987-06-06

Family

ID=31121752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17904785U Pending JPS6289038U (en) 1985-11-22 1985-11-22

Country Status (1)

Country Link
JP (1) JPS6289038U (en)

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