JPS6286892A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPS6286892A JPS6286892A JP22819585A JP22819585A JPS6286892A JP S6286892 A JPS6286892 A JP S6286892A JP 22819585 A JP22819585 A JP 22819585A JP 22819585 A JP22819585 A JP 22819585A JP S6286892 A JPS6286892 A JP S6286892A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- hole
- resist
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は、プリント配線基板の製造方法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for manufacturing a printed wiring board.
(従来の技術)
従来よりプリント配線基板の製造方法には、種々の方法
があるが、大別するとサブトラクティブ法とアディティ
法がある。サブトラクティブ法は極めて高度に開発され
た方法で、現在量も普及しているプリント配線基板の製
造方法である。(Prior Art) Conventionally, there are various methods for manufacturing printed wiring boards, and they can be broadly classified into subtractive methods and adity methods. The subtractive method is an extremely highly developed method and is currently a widely used method for manufacturing printed wiring boards.
このサブトラクティブ法の工程を第2図ax gによっ
て説明すると、先ず第2図aに示すCu 7f31aを
両面に張った積層基板1の所要位置に第2図すの如く穴
2をあける。次にこの穴2をあけた基板1に第2図Cに
示す如くスルホールCuめっきを施して、基板の1の両
面のCu箔1a及び穴2の内面にCuめっき層3を形成
する。次いでこのスルホールCuめっきを施した基(反
1の両面のCuめっき層3に第2図dに示す如く所要の
配線パターンを形成するホトレジスト4を設ける。次に
このホトレジスト4をプリントした基1反1に第2図e
に示す如<Auめっきを施す。次いで基板l上のホトレ
ジスト4を第2図fに示す如く剥離する。然る後第2図
gに示す如くエツチングを行ってAuめっき5以外の部
分のCuめっき居3及びCuFglaを除去して、所要
の配線6を形成する。The steps of this subtractive method will be explained with reference to FIG. 2, ax to g. First, holes 2 are made as shown in FIG. 2 at desired positions in the laminated substrate 1 shown in FIG. Next, as shown in FIG. 2C, through-hole Cu plating is applied to the substrate 1 having the holes 2 formed therein, thereby forming a Cu plating layer 3 on the Cu foil 1a on both sides of the substrate 1 and on the inner surface of the hole 2. Next, a photoresist 4 for forming a required wiring pattern as shown in FIG. 1 and Figure 2 e
Apply Au plating as shown in . Next, the photoresist 4 on the substrate 1 is peeled off as shown in FIG. 2f. Thereafter, as shown in FIG. 2g, etching is performed to remove the Cu plating 3 and CuFgla in areas other than the Au plating 5, thereby forming the required wiring 6.
(発明が解決しようとする問題点)
ところで、上記従来のサブトラクティブ法によるプリン
ト配線基板の製造方法では、配線パターン中例えば穴2
の内面や周縁などに不必要なAuめっき5が施されるの
で、高価なAuが無駄に使用されるものである。(Problems to be Solved by the Invention) By the way, in the conventional method for manufacturing a printed wiring board using the subtractive method described above, for example, holes 2 in the wiring pattern are
Since unnecessary Au plating 5 is applied to the inner surface and the periphery, expensive Au is wasted.
そこで本発明は、配線パターン中例えば穴の内面や周縁
などに不必要なAuめっきを施さないようにしたプリン
ト配線基板の製造方法を提供しようとするものである。SUMMARY OF THE INVENTION Therefore, the present invention provides a method for manufacturing a printed wiring board in which unnecessary Au plating is not applied to the wiring pattern, such as the inner surface or periphery of a hole.
(問題点を解決するための手段)
上記問題点を解決するための本発明によるプリント配線
基板の製造方法は、Cu箔張積層基板の所要位置に穴あ
けをした後スルホールCuめっきを施し、次にこの基板
の両面に穴を塞ぎ且つ所要のAuめっき配線パターンを
形成する第ルジス・トを設け、次いで基板にAuめっき
を施し次に第1レジストを剥離し、次いで基板の両面に
穴を塞ぎ且つ所要の配線パターンを形成する第2レジス
トを設け、次にエツチングを行い、然る後第2レジスト
を剥η1【シて配線を形成することを特徴とする。(Means for Solving the Problems) In order to solve the above problems, the method for manufacturing a printed wiring board according to the present invention involves drilling holes at required positions in a Cu foil-clad laminate board, then applying through-hole Cu plating, and then A first resist is provided on both sides of this substrate to close the hole and form the required Au plating wiring pattern, then Au plating is applied to the substrate, the first resist is peeled off, and then the hole is closed on both sides of the substrate. The method is characterized in that a second resist for forming a desired wiring pattern is provided, then etching is performed, and then the second resist is peeled off to form wiring.
(作用)
上記のように本発明のプリント配線基板の製造方法では
、スルホールCuめっきを施した後、基板の両面のCu
めっき層に穴を塞ぎ且つAuめっき配線パターンを形成
する第1レジストを設けるので、基板にAuめっきを施
した際、例えばスルホールの内面や周縁などに不必要な
Auめっきが施されてない。またエツチングする際、基
板の両面に穴を塞ぐ第2レジストを設けるので、エツチ
ングによって穴の内面及び周縁のCuめっき層、Cu箔
が除去されることがない。(Function) As described above, in the method for manufacturing a printed wiring board of the present invention, after performing through-hole Cu plating, Cu plating on both sides of the board is performed.
Since the first resist that closes the holes and forms the Au plating wiring pattern is provided in the plating layer, when the substrate is plated with Au, unnecessary Au plating is not applied to, for example, the inner surface or the periphery of the through hole. Furthermore, during etching, since a second resist is provided on both sides of the substrate to close the hole, the Cu plating layer and Cu foil on the inner surface and periphery of the hole are not removed by etching.
(実施例)
本発明によるプリント配線基板の製造方法の一実施例を
第1図a乃至iによって説明する。先ず第1図aに示す
Cu箔1aを両面に張った積N基板1の所要位置に第1
図すに示す如く穴2をあける。次にこの穴2をあけた基
板1に第1図Cに示す如(スルホールCuめっきを施し
て、基板1の両面のCuFgla及び穴2の内面にCu
めっき層3を形成する。次に基板1の両面に感光性ドラ
イフィルムを貼り、これを露光、現像して、第1図dに
示す如く穴2を塞ぎ且つ所要のAuめっき配線パターン
を形成する第1レジスト4′を設ける。(Example) An example of the method for manufacturing a printed wiring board according to the present invention will be described with reference to FIGS. 1a to 1i. First, a first plate is placed at a predetermined position on a multilayer substrate 1 with Cu foil 1a stretched on both sides as shown in FIG. 1a.
Drill a hole 2 as shown in the figure. Next, as shown in FIG.
A plating layer 3 is formed. Next, a photosensitive dry film is applied to both sides of the substrate 1, and this is exposed and developed to form a first resist 4' that closes the hole 2 and forms the required Au plating wiring pattern as shown in FIG. 1d. .
次に基板1の両面に該1図eに示す如(Auめっき5を
施す。次いで基板1上の第1レジスト4′を第1図fに
示す如く剥離する。次にこの基板lの両面に感光性ドラ
イフィルムを貼り、これを露光、現像して、第1図gに
示す如(穴2を塞ぎ所要の配線パターンを形成する第2
レジスト4“を設ける。次いで第1図りに示す如くエツ
チングを行ってAuめっき層5及び第2レジスト4“以
外の部分のCuめっき層3及びCu箔1aを除去し、然
る後第1図iに示す如く第2レジスト4“を剥離して所
要の配線6を形成する。Next, Au plating 5 is applied to both sides of the substrate 1 as shown in FIG. 1e. Next, the first resist 4' on the substrate 1 is peeled off as shown in FIG. A photosensitive dry film is pasted, exposed and developed to form a second film that closes the hole 2 and forms the required wiring pattern, as shown in Figure 1g.
A resist 4" is provided. Next, as shown in the first figure, etching is performed to remove the Cu plating layer 3 and the Cu foil 1a other than the Au plating layer 5 and the second resist 4". As shown in FIG. 2, the second resist 4'' is peeled off to form the required wiring 6.
上記実施例の通り本発明のプリント配線基板の製造方法
では、穴2をあけたCu箔1aの張りの積層基板1にス
ルホールCuめっきを施した後、基板1の両面のCuめ
っき層3上に穴2を塞ぎ且つ所要のAuめっき配線パタ
ーンを形成する第1レジスト4′を設けるので、Auめ
っき5を施した際、穴2の内面や周縁などに不必要なA
uめっき5が施されることがない。またエツチングする
際、基板lの両面に穴2を塞ぐ第2レジスト4“を設け
るので、エツチングによって穴2の内面及び周縁のCu
めっき層3、Cu箔1aが取り除かれることがない。As in the above embodiment, in the method for manufacturing a printed wiring board of the present invention, after through-hole Cu plating is applied to the laminated board 1 made of Cu foil 1a with holes 2, the Cu plating layer 3 on both sides of the board 1 is coated. Since the first resist 4' is provided to close the hole 2 and form the required Au plating wiring pattern, unnecessary A is removed from the inner surface and periphery of the hole 2 when the Au plating 5 is applied.
U plating 5 is not applied. Furthermore, when etching, since a second resist 4'' is provided on both sides of the substrate l to close the hole 2, the etching removes the Cu on the inner surface and the periphery of the hole 2.
The plating layer 3 and the Cu foil 1a are not removed.
(発明の効果)
以上詳細した通り本発明のプリント配線基板の製造方法
は、Auめっきする際、第1レジストにより穴を塞ぎ且
つAuめっきの必要な配線部分以外の配線部分、穴の内
面及び周縁に不必要なAuめっきが施されない。従って
、高価なAuが無駄に使用されることが無いので、プリ
ント配線基板の製造費を低減できる。また穴の内面及び
周縁にAuめっきが施されなくともエツチングする際、
基板の穴を第2レジストにより塞ぐので、穴の内面及び
周縁のCuめっき層、Cu箔が除去されることがないの
で、ターミナルの装着に何ら支障がなく、品質良好なプ
リント配線基板を製造できる。(Effects of the Invention) As described in detail above, the method for manufacturing a printed wiring board of the present invention is such that when performing Au plating, the hole is closed with the first resist, and the wiring portion other than the wiring portion that requires Au plating, the inner surface and the periphery of the hole. No unnecessary Au plating is applied to the surface. Therefore, since expensive Au is not wasted, the manufacturing cost of the printed wiring board can be reduced. Also, when etching, even if the inner surface and periphery of the hole are not plated with Au,
Since the hole in the board is closed with the second resist, the Cu plating layer and Cu foil on the inner surface and periphery of the hole are not removed, so there is no problem in mounting the terminal, and a high-quality printed wiring board can be manufactured. .
第1図a乃至iは本発明によるプリント配線基板の製造
方法の工程を示す断面図、第2図a乃至gは従来のサブ
トラクティブ法のプリント配線基板の製造方法の工程を
示す要部断面図である。
出願人 田中貴金属工業株式会社
第1図
2・・・代 5・・・ALLめう
き第1図
6・・・ 白己穣1A to 1I are cross-sectional views showing the steps of the printed wiring board manufacturing method according to the present invention, and FIGS. 2A to 2G are main part sectional views showing the steps of the conventional subtractive method of manufacturing the printed wiring board. It is. Applicant Tanaka Kikinzoku Kogyo Co., Ltd. Figure 1 2... Generation 5... ALL Meuki Figure 1 6... Shiraki Jo
Claims (1)
ルCuめっきを施し、次にこの基板の両面に穴を塞ぎ且
つ所要のAuめっき配線パターンを形成する第1レジス
トを設け、次いで基板にAuめっきを施し、次に第1レ
ジストを剥離し、次いで基板の両面に穴を塞ぎ且つ所要
の配線パターンを形成する第2レジストを設け、次にエ
ッチングを行い、然る後第2レジストを剥離して配線を
形成するプリント配線基板の製造方法。After drilling holes in the required positions of the Cu foil-clad laminate board, through-hole Cu plating is applied, then a first resist is provided on both sides of this board to close the holes and form the required Au plating wiring pattern, and then Au plating is applied to the board. Then, the first resist is peeled off, a second resist is provided on both sides of the substrate to close the holes and form the required wiring pattern, and then etching is performed, and then the second resist is peeled off to form the wiring pattern. A method for manufacturing a printed wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22819585A JPS6286892A (en) | 1985-10-14 | 1985-10-14 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22819585A JPS6286892A (en) | 1985-10-14 | 1985-10-14 | Manufacture of printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6286892A true JPS6286892A (en) | 1987-04-21 |
Family
ID=16872692
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22819585A Pending JPS6286892A (en) | 1985-10-14 | 1985-10-14 | Manufacture of printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6286892A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54102567A (en) * | 1978-01-27 | 1979-08-13 | Hitachi Chemical Co Ltd | Method of producing doubleesided through hole printed circuit |
JPS54104569A (en) * | 1978-02-03 | 1979-08-16 | Shindo Denshi Kougiyou Kk | Method of producing flexible printed circuit to be partially plated |
-
1985
- 1985-10-14 JP JP22819585A patent/JPS6286892A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54102567A (en) * | 1978-01-27 | 1979-08-13 | Hitachi Chemical Co Ltd | Method of producing doubleesided through hole printed circuit |
JPS54104569A (en) * | 1978-02-03 | 1979-08-16 | Shindo Denshi Kougiyou Kk | Method of producing flexible printed circuit to be partially plated |
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