JPS6286864A - Manufacture of soi structure misfet - Google Patents
Manufacture of soi structure misfetInfo
- Publication number
- JPS6286864A JPS6286864A JP22904885A JP22904885A JPS6286864A JP S6286864 A JPS6286864 A JP S6286864A JP 22904885 A JP22904885 A JP 22904885A JP 22904885 A JP22904885 A JP 22904885A JP S6286864 A JPS6286864 A JP S6286864A
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- single crystal
- polysilicon layer
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000013078 crystal Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000010030 laminating Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 11
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 239000004952 Polyamide Substances 0.000 claims 1
- 229920002647 polyamide Polymers 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052786 argon Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000004299 exfoliation Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002250 progressing effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体の集積度を向上させるために５ｏｌ（Ｓｔ−１ｉ
ｃｏｎ Ｏｎ Ｉｎ５ｕｌａｔｏｒ ）、即ち３次
元集積回路の開発が進んでいるが、通常３次元にシリコ
ンを積層するための絶縁層としては酸化膜、窒化膜等が
使用される。本発明では絶縁層として酸化膜と窒化膜よ
りなる２層構造を用い、剥離対して強く、且つトランジ
スタ特性の良好なるＳｏｌ構造のＭＩＳＦＥＴの製造方
法を述べる。[Detailed Description of the Invention] [Summary] In order to improve the degree of integration of semiconductors, 5ol (St-1i
The development of three-dimensional integrated circuits (con-on-insulators) is progressing, and oxide films, nitride films, etc. are usually used as insulating layers for three-dimensionally stacking silicon. The present invention describes a method for manufacturing a MISFET having a Sol structure that is resistant to peeling and has good transistor characteristics, using a two-layer structure consisting of an oxide film and a nitride film as an insulating layer.
本発明は、Ｓｏｌ構造よりなるＭＩＳＦＥＴの製造方法
に関する。The present invention relates to a method for manufacturing a MISFET having a Sol structure.
Ｓｏｌ構造は、各トランジスタ素子が従来のごとく平面
的に形成されるのでなく、絶縁膜を介して立体的に３次
元に形成される。In the Sol structure, each transistor element is not formed two-dimensionally as in the conventional case, but three-dimensionally formed three-dimensionally with an insulating film interposed therebetween.
これにより集積度が著しく向上するのみならず、浮遊容
量も減少し、隣接素子との絶縁の問題も解決する新しい
技術であり、集積回路の高集積化と性能の向上に寄与す
る所大であるので開発が進みつつある。This is a new technology that not only significantly improves the degree of integration, but also reduces stray capacitance and solves the problem of insulation with adjacent elements, making it a major contribution to higher integration and improved performance of integrated circuits. Therefore, development is progressing.
このようなＳＯＩ構造は、一般に絶縁膜として酸化膜（
Ｓｉｎ、膜）が用いられる。これは絶縁膜上に形成され
るシリコンの単結晶化領域との界面特性が良好であるこ
とによるが、機械的には剥離に対して弱い欠点があり改
善が要望されている。Such an SOI structure generally uses an oxide film (
Sin, film) is used. This is due to the good interface characteristics with the single crystalline silicon region formed on the insulating film, but mechanically it has the drawback of being weak against peeling, and improvements are desired.
Ｓｏｌの基本的な問題として、絶縁膜上に半導体単結晶
層を形成することが必要である。その一方法を絶縁膜と
してＳｉＯ□膜を用いる例について説明する。５ｉＯｚ
はシリコン半導体に最もよく用いられる絶縁膜でシリコ
ンとの界面特性は良い材料として知られている。A fundamental problem with Sol is that it is necessary to form a semiconductor single crystal layer on an insulating film. One method will be described using an example in which an SiO□ film is used as the insulating film. 5iOz
is the most commonly used insulating film for silicon semiconductors, and is known to have good interfacial properties with silicon.
第２図（ａ）に示すごとくシリコン基板１に５ｆＣｈ膜
２を積層する。その上にポリシリコン層３を積層し、レ
ーザあるいは電子ビームを照射、走査してポリシリコン
層を一旦溶融し、これを冷却再結晶化することにより単
結晶領域４を形成する。As shown in FIG. 2(a), a 5fCh film 2 is laminated on a silicon substrate 1. A polysilicon layer 3 is laminated thereon, the polysilicon layer is once melted by irradiation and scanning with a laser or an electron beam, and the single crystal region 4 is formed by cooling and recrystallizing the polysilicon layer.
この単結晶化領域を形成するに当たって、シードと呼ば
れる種結晶を必要とし、これを核として単結晶を引き延
ばして形成するが、上記の例ではこのシードをポリシリ
コン層３内に新たに作った場合について説明している。In forming this single crystallized region, a seed crystal called a seed is required, and the single crystal is stretched using this as a core. In the above example, when this seed is newly created within the polysilicon layer 3, is explained.
この単結晶成長を容易とするため、反射防止膜をポリシ
リコン層の上に積層する方法が多く用いられているが本
発明とは直接関係がないので省略する。In order to facilitate this single crystal growth, a method of laminating an antireflection film on a polysilicon layer is often used, but this method is omitted since it is not directly related to the present invention.
このようにして形成された単結晶領域は、大きさとして
は幅数１０μｍ３長さ数１００Ｉ！ｍ以下ではあるがト
ランジスタを形成するには充分の広さを持つ。The single crystal region thus formed has a width of several 10 μm and a length of several 100 I! Although it is less than m, it is large enough to form a transistor.
単結晶領域４を、ＭＯＳ Ｆ ＥＴを形成するに必要な
る領域を残して除去し、その後、ゲート酸化膜５、ゲー
ト電極６、ソース領域７、ドレイン領域８等を形成する
工程を通常のＭＯＳ Ｆ ＥＴの製造方法と同様に行う
。その結果を第２図（ｂｌにその断面形状で示す。The single crystal region 4 is removed except for the region necessary to form a MOS FET, and then the steps of forming a gate oxide film 5, a gate electrode 6, a source region 7, a drain region 8, etc. are performed using a normal MOS FET. It is carried out in the same manner as the manufacturing method of ET. The results are shown in cross-sectional shape in Figure 2 (bl).
上記に述べた、従来の技術によるＳ ｉ Ｏｚ膜上にポ
リシリコン層を積層し、例えばレーザを照射して単結晶
化する方法では、単結晶シリコンと下地のＳｉＯ□膜と
の密着性が劣ることである。In the method described above, in which a polysilicon layer is laminated on a SiOz film using the conventional technique, and the polysilicon layer is made into a single crystal by, for example, laser irradiation, the adhesion between the single crystal silicon and the underlying SiO□ film is poor. That's true.
このため剥離の問題を発生して、工程での歩留りの低下
を来す。This causes a problem of peeling, resulting in a decrease in yield in the process.
絶縁膜としては５ｉｚＮ４膜の方がぬれ係数の違いで剥
離しにくい。然し単結晶シリコンとの界面特性が劣るた
めトランジスタの特性が５ｉＯｚ膜の場合に比して劣る
。As an insulating film, the 5izN4 film is less likely to peel off due to the difference in wetting coefficient. However, since the interface characteristics with single crystal silicon are poor, the characteristics of the transistor are inferior to those of a 5iOz film.
更に、Ｓ ｉ ＣＩ Ｎ ４膜は、その膜厚が厚くなる
とストレスが残るので２０００Å以上の膜厚では良い絶
縁膜を形成することが出来ない等の問題があり、通常は
ＳＯＩの絶縁膜としては単独では使い難い。Furthermore, as the SiCIN4 film becomes thicker, stress remains, so a good insulating film cannot be formed with a film thickness of 2000 Å or more. Difficult to use alone.
上記問題点は、基板上に酸化膜、次いで窒化膜の２層を
積層し、該窒化膜にはその上に形成すべきトランジスタ
のチャネルに相当する領域に溝を開口して前記酸化膜を
露出せしめた後、ポリシリコン層を積層する。The above problem is solved by laminating two layers, an oxide film and then a nitride film, on a substrate, and exposing the oxide film by opening a groove in the nitride film in a region corresponding to the channel of a transistor to be formed on the nitride film. After this, a polysilicon layer is laminated.
しかる後、該ポリシリコン層にエネルギー線の照射を加
えてグレイン・バウンダリー・７１７−の単結晶領域を
形成する。Thereafter, the polysilicon layer is irradiated with energy rays to form a single crystal region with a grain boundary 717-.
更に、該単結晶領域に前記溝の上部をチャネルとするト
ランジスタを形成することよりなる本発明のＳＯＩ構造
ＭＩＳＦＥＴの製造方法によって解決される。Furthermore, the problem is solved by the method of manufacturing an SOI structure MISFET of the present invention, which comprises forming a transistor in the single crystal region with the upper part of the groove as a channel.
本発明ではｓｏｒの絶縁膜として、ＳｉＯ□膜、Ｓ ｉ
３ Ｎ ４膜の特徴をそれぞれ活かすことを目的とし
ている。In the present invention, as the sor insulating film, SiO□ film, Si
The purpose is to take advantage of the characteristics of each of the 3N4 films.
溝の部分を除いて大部分は薄い５ｉｚＮａ膜で覆われて
いるのでレーザ・アニールによる剥がれは殆ど防止され
る。Since most of the film except for the grooves is covered with a thin 5izNa film, peeling due to laser annealing is almost prevented.
一方、トランジスタとしての特性に著しく影客を与える
チャネル領域は、５１３Ｎ４膜に露出せるＳｉＯ□膜上
の界面特性の良い単結晶領域に形成されているので、し
きい値電圧の変動、あるいはソース、ドレイン間のリー
ク等の特性上の問題は回避出来る。On the other hand, the channel region, which significantly affects the characteristics of the transistor, is formed in a single crystal region with good interface characteristics on the SiO□ film exposed to the 513N4 film. Characteristic problems such as leakage between drains can be avoided.
〔実施例〕 本発明の一実施例を図面により詳細説明する。〔Example〕 An embodiment of the present invention will be described in detail with reference to the drawings.
第１図ｆａ）〜（ｄｌは本発明による製造方法を工程順
に断面図で示す。FIGS. 1fa) to 1dl are cross-sectional views showing the manufacturing method according to the present invention in the order of steps.
シリコン基板１上に、熱酸化法によりＳｉＯ□膜２を約
１μｍ成長させる。次いでＣＶＤ法によりＳ ｉ ３’
Ｎ ４膜９を約３００人積層する。これを第１図（ａｌ
に示す。A SiO□ film 2 is grown to a thickness of about 1 μm on a silicon substrate 1 by thermal oxidation. Then, by CVD method, S i 3'
About 300 people stack the N4 film 9. This is shown in Figure 1 (al
Shown below.
次いで、フォトリソグラフィ法によりこれらの絶縁膜上
に形成するトランジスタのチャネル領域に相当する領域
に対して、Ｓｉ３Ｎｍ膜９に溝１０を開口して、ＳｉＯ
□膜２を露出せしめる。これを第１図（ｂ）に示す。Next, a trench 10 is opened in the Si3Nm film 9 in a region corresponding to a channel region of a transistor to be formed on these insulating films by photolithography, and a SiO
□Expose the membrane 2. This is shown in FIG. 1(b).
通常、高集積回路ではチャネル長は１〜２μｍ程度であ
るので、′ａ１０の幅は多少マスク合わせの余裕をみて
２〜３μｍに選ばれる。Normally, in highly integrated circuits, the channel length is about 1 to 2 .mu.m, so the width of 'a10 is selected to be 2 to 3 .mu.m, taking into account some margin for mask alignment.
以上のごとく絶縁層を積層せる基板にポリシリコン層３
を約５０００人成長させる。これを第１図（Ｃ）に示す
。As described above, a polysilicon layer 3 is formed on the substrate on which the insulating layer is laminated.
to grow by approximately 5,000 people. This is shown in FIG. 1(C).
上記基板にアルゴン・イオン・レーザを照射しつつ、走
査して２旦ポリシリコンを溶融し、冷却の過程でグレイ
ン・パウンダリー・フリーの単結晶領域を成長させる。While irradiating the substrate with an argon ion laser, the polysilicon is melted twice by scanning, and a grain/poundage-free single crystal region is grown during the cooling process.
５ｉｌＮ４膜９の厚さは３００人と充分薄く積層されて
いるので、Ｓｉ３Ｎ、膜の溝１０によって形成される段
差は極めて僅かであり、上記の再結晶化工程では殆ど悪
影響を受けない。Since the thickness of the 5ilN4 film 9 is 300, which is a sufficiently thin layer, the step formed by the grooves 10 in the Si3N film is extremely small and is hardly adversely affected by the above-mentioned recrystallization process.
ポリシリコン層の大部分はＳｉ、Ｎ、膜９の上で再結晶
領域が拡がるので剥離に対しては強い単結晶領域が形成
される。Most of the polysilicon layer has Si, N, and the recrystallized region expands on the film 9, so that a single crystal region that is resistant to peeling is formed.
以後、必要なるトランジスタ領域をパターンニングして
、溝１０の上にチャネル領域が形成出来るごとくゲート
酸化膜５、ゲート電極６を形成し、ソース領域７、ドレ
イン領域８を形成して３次元構造の集積回路を形成する
。これを第１（ｄ）に示す。Thereafter, necessary transistor regions are patterned, gate oxide film 5 and gate electrode 6 are formed so that a channel region can be formed on trench 10, and source region 7 and drain region 8 are formed to form a three-dimensional structure. form integrated circuits; This is shown in Section 1(d).
以上に説明せるごとく本発明によるＳＯＩ構造のＭＩＳ
ＦＥＴの製造方法により、剥離に対して強い絶縁膜上の
シリコン層を形成することが可能となり、且つそこに形
成されたトランジスタの特性を劣化させることもない。As explained above, the SOI structure MIS according to the present invention
The FET manufacturing method makes it possible to form a silicon layer on an insulating film that is resistant to peeling, and does not deteriorate the characteristics of a transistor formed there.
第１図（ａｌ 〜（ｄ）は本発明にかかわるＭＩＳＦＥ
Ｔの製造方法を説明する工程順断面図、
第２図（ａｌ、 （ｂ）は従来の技術によるＭＯＳ Ｆ
ＥＴの製造方法を説明する断面図、
を示す。
図面において、
１はシリコン基板、
２は酸化膜（Ｓ ｉ Ｏｚ膜）、
３はポリシリコン層、
４は単結晶領域、
５はゲート酸化膜、
６はゲート電極、
７はソース領域、
８はドレイン領域、
９は窒化膜（Ｓ ｉ ３ Ｎ ４膜）、１０は溝、
をそれぞれ示す。
言え日月Ｔ３ｒ−ネｆ Ｉｆｆ！ ＃面凹第１図
第１図
第２図FIG. 1 (al to (d)) shows the MISFE according to the present invention.
2(a) and 2(b) are cross-sectional views in order of steps explaining the manufacturing method of MOS F
A cross-sectional view illustrating a method for manufacturing ET is shown. In the drawings, 1 is a silicon substrate, 2 is an oxide film (SiOz film), 3 is a polysilicon layer, 4 is a single crystal region, 5 is a gate oxide film, 6 is a gate electrode, 7 is a source region, and 8 is a drain 9 is a nitride film (S i 3 N 4 film), and 10 is a groove. Saye Kazuki T3r-Nef If! # Concave surface Fig. 1 Fig. 2
Claims (1)
層し、該窒化膜に溝（１０）を開口して前記酸化膜を露
出せしめた後、ポリシリコン層（３）を積層する工程と
、該ポリシリコン層にエネルギー線の照射を加えてグレ
イン・バウンダリー・フリーの単結晶領域を形成する工
程と、 該単結晶領域に前記溝（１０）の上部をチャネルとする
トランジスタを形成する工程を含むことを特徴とするＳ
ＯＩ構造ＭＩＳＦＥＴの製造方法。[Claims] An oxide film (2) and then a nitride film (9) are laminated on a substrate (1), a groove (10) is opened in the nitride film to expose the oxide film, and then a polyamide film is formed. a step of laminating a silicon layer (3); a step of irradiating the polysilicon layer with energy rays to form a grain boundary-free single crystal region; S characterized by comprising the step of forming a transistor having a channel of
A method for manufacturing an OI structure MISFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22904885A JPH0682685B2 (en) | 1985-10-14 | 1985-10-14 | Method for manufacturing SOI structure MISFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22904885A JPH0682685B2 (en) | 1985-10-14 | 1985-10-14 | Method for manufacturing SOI structure MISFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6286864A true JPS6286864A (en) | 1987-04-21 |
| JPH0682685B2 JPH0682685B2 (en) | 1994-10-19 |
Family
ID=16885927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22904885A Expired - Lifetime JPH0682685B2 (en) | 1985-10-14 | 1985-10-14 | Method for manufacturing SOI structure MISFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682685B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4950618A (en) * | 1989-04-14 | 1990-08-21 | Texas Instruments, Incorporated | Masking scheme for silicon dioxide mesa formation |
-
1985
- 1985-10-14 JP JP22904885A patent/JPH0682685B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4950618A (en) * | 1989-04-14 | 1990-08-21 | Texas Instruments, Incorporated | Masking scheme for silicon dioxide mesa formation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0682685B2 (en) | 1994-10-19 |
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