JPH01128574A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01128574A JPH01128574A JP62285438A JP28543887A JPH01128574A JP H01128574 A JPH01128574 A JP H01128574A JP 62285438 A JP62285438 A JP 62285438A JP 28543887 A JP28543887 A JP 28543887A JP H01128574 A JPH01128574 A JP H01128574A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- single crystal
- insulating layer
- forming
- soi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 239000013078 crystal Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000005224 laser annealing Methods 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 14
- 238000005468 ion implantation Methods 0.000 abstract description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 229910052786 argon Inorganic materials 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000009751 slip forming Methods 0.000 abstract 1
- 238000001953 recrystallisation Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- -1 nitrogen ions Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
〔概 要］
本発明は半導体装置の製造方法に係り、特にレーザ再結
晶ＳＯＩ技術と、０°イオン注入技術でシート部分を選
択的にＳｏｌ化する技術（ＳＩＭＯＸ技術）とを用いた
ＳＯＩ／ＭＯＳＦＥＴの製造方法に関し、本発明はレー
ザ再結晶ＳＯＩ技術を用いても集積度が低下しないＭＯ
ＳＦＥＴを製造することを目的とし、
下記（イ）−（、ｌ工程：
（イ） 単結晶シリコン基板上に絶縁層を形成する工
程、
（ｏ） 該デバイス形成領域内でしかもチャネル領域
以外の領域にある該絶縁層部にレジストを用いて単結晶
成長用の窓開けを行なう工程、（ＩＮ 該レジストを
残存、させた状態で多結晶シリコン層を全露出面に形成
する工程、
（勾 リフトオフ技術により前記残存レジスト及び該レ
ジスト上の多結晶シリコン層を除去した後全面に第２の
多結晶シリコン層を形成する工程、休） レーザアニー
ル処理により前記第１の多結晶シリコン層全体を単結晶
化する工程、（→ 前記シート部に選択的に０゛イオン
を注入し、アニール処理を行なう工程、
を含むことを構成とする。[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, and in particular a method for selectively turning a sheet portion into Sol using a laser recrystallization SOI technology and a 0° ion implantation technology (SIMOX technology). The present invention relates to a method for manufacturing an SOI/MOSFET using
For the purpose of manufacturing an SFET, the following steps (a)-(,l) are performed: (a) a step of forming an insulating layer on a single crystal silicon substrate; (o) a region within the device formation region and other than the channel region; A process of opening a window for single crystal growth using a resist in the insulating layer part (IN) A process of forming a polycrystalline silicon layer on the entire exposed surface with the resist remaining (IN) A process of forming a polycrystalline silicon layer on the entire exposed surface with the resist remaining (IN) Step of forming a second polycrystalline silicon layer on the entire surface after removing the remaining resist and the polycrystalline silicon layer on the resist by laser annealing. (→ a step of selectively implanting 0° ions into the sheet portion and performing an annealing treatment.
Ｃ産業上の利用分野〕
本発明は半導体装置の製造方法に係り、特にレーザ再結
晶ＳＯＩ技術と、０°イオン注入技術でシート部分を選
択的にｓｏｒ化する技術（ＳＩＭＯＸ技術）とを用いた
ＳＯＩ／ＭＯ３ＦＥＴの製造方法に関する。C. Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method using a laser recrystallization SOI technology and a technology for selectively converting a sheet portion into sor using a 0° ion implantation technology (SIMOX technology). The present invention relates to a method for manufacturing SOI/MO3FET.
［従来の技術］
ＳＯＩ （Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｉｎ
ｇ ５ｕｂｓｔｒａｔｅ）構造はバルク結晶内に酸素や
窒素をイオン注入し内部に絶縁層を形成し、絶縁層を介
して単結晶層が分離された構造をとるものである。[Conventional technology] SOI (Silicon On Insulatin)
The structure (g5ubstrate) has a structure in which oxygen or nitrogen ions are implanted into a bulk crystal to form an insulating layer therein, and a single crystal layer is separated via the insulating layer.
従来種結晶（シート）を有するシリコン基板上に多結晶
シリコンをＣＶＤ法等で堆積した後、レーザアニールに
よって多結晶シリコンを種結晶の持つ結晶方位と同一方
位の単結晶に再結晶させるいわゆるレーザ再結晶Ｓｏｌ
技術を用いてＭＯＳ ）ランジスタ等のデバイスを製造
する方法が知られている。Conventionally, polycrystalline silicon is deposited on a silicon substrate having a seed crystal (sheet) by a CVD method, and then the polycrystalline silicon is recrystallized into a single crystal with the same crystal orientation as that of the seed crystal by laser annealing. Crystal Sol
Methods of manufacturing devices such as MOS (MOS) transistors using technology are known.
Ｃ発明が解決しようとする問題点〕
従来のレーザ再結晶Ｓｏｌ技術を用いてデバイスを製造
するにはシート部分をソース、ドレイン領域等のデバイ
ス形成領域以外に形成する必要があり、シート部分同志
の距離が数十μｍ程度にもなりデバイスの集積度を低下
させ、しかもシート部分からの単結晶成長が１０〜２０
μｍ程度で停止して、絶縁層上の全多結晶シリコンを均
一に再結晶化することが出来なかった。C Problems to be Solved by the Invention] In order to manufacture devices using the conventional laser recrystallization Sol technology, it is necessary to form sheet portions in areas other than device formation regions such as source and drain regions, and The distance is on the order of tens of micrometers, reducing the degree of device integration, and single crystal growth from the sheet portion is 10 to 20 μm.
It stopped at about μm, and it was not possible to uniformly recrystallize all the polycrystalline silicon on the insulating layer.
また集積度を低下させないようにシート部分をデバイス
領域内に形成するとシート部分が凹部となり段差を形成
し、しかもＳｏｌ構造にならないので容量的にＳＯＩの
利点を生かせない問題があった。Furthermore, if the sheet portion is formed within the device region so as not to reduce the degree of integration, the sheet portion becomes a recess, forming a step, and furthermore, the Sol structure is not formed, so there is a problem in that the advantages of SOI cannot be utilized in terms of capacitance.
本発明はレーザ再結晶Ｓｏｌ技術を用いても集積度が低
下しない？１Ｏ５ＦＥＴを製造することを目的とする。Does the present invention not reduce the degree of integration even if laser recrystallization Sol technology is used? The purpose is to manufacture 1O5FET.
上記問題点は本発明によれば、
（イ） 単結晶シリコン基板上に絶縁層を形成する工程
、
（０）該デバイス形成領域内でしかもチャネル領域以外
の領域にある該絶縁層部にレジストを用いて単結晶成長
用の窓開けを行なう工程、＆９ 該レジストを残存させ
た状態で第１の多結晶シリコン層を全露出面に形成する
工程、に） リフトオフ技術により前記残存レジスト及
び該レジスト上の多結晶シリコン層を除去した後、全面
に第２の多結晶シリコン層を形成する工程、体） レー
ザアニール処理により前記第１の多結晶シリコン層全体
を単結晶化する工程、（→ 前記シート部に選択的に０
″″イオンを注入し、アニール処理を行なう工程、
を含む半導体製造方法によって解決される。According to the present invention, the above-mentioned problems can be solved by: (a) forming an insulating layer on a single crystal silicon substrate; (0) applying a resist to the insulating layer in the device formation region and in a region other than the channel region; (9) forming a first polycrystalline silicon layer on the entire exposed surface with the resist remaining; a step of forming a second polycrystalline silicon layer on the entire surface after removing the polycrystalline silicon layer; a step of converting the entire first polycrystalline silicon layer into a single crystal by laser annealing; selectively 0
The problem is solved by a semiconductor manufacturing method including the steps of implanting ions and performing an annealing process.
本発明によれば従来のレーザ再結晶ＳＯＩ技術と０゛イ
オン注入による絶縁層の形成（ＳＩＭＯＸ技術）により
シートをデバイス内に形成して集積化された浮遊容量を
低減した５ロ）７ＭＯ５ＦＥＴの製造を可能にする。According to the present invention, a 7 MO5FET is manufactured using conventional laser recrystallization SOI technology and the formation of an insulating layer by ion implantation (SIMOX technology) to form a sheet in the device to reduce the integrated stray capacitance. enable.
以下本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図から第６Ａ図は本発明の製造工程を説明するため
の断面図であり、そのうち第３Ｂ図は第３Ａ図の模式平
面図であり、第６Ｂ図は第６Ａ図の模式平面図である。1 to 6A are cross-sectional views for explaining the manufacturing process of the present invention, of which FIG. 3B is a schematic plan view of FIG. 3A, and FIG. 6B is a schematic plan view of FIG. 6A. be.
第１図に示すようにＳ ｉ （１００）基板１上に約４
０００人の厚さの５ｉロ）からなる絶縁層２をＣＶＤ（
化学的気相成長）法により成長させた後、該絶縁Ｍｌ上
にレジスト３を塗布後バターニングし該レジスト３をマ
スクとしてＲＩＢ等のドライエツチングによりシート部
Ａ、Ｂの窓４を開けを行ないＳｉ基板を一部露出する。As shown in FIG.
The insulating layer 2 consisting of 5.000 mm thick (5i) is deposited by CVD (
After growth by chemical vapor deposition), a resist 3 is coated on the insulating Ml and then buttered, and windows 4 in the sheet parts A and B are opened by dry etching such as RIB using the resist 3 as a mask. Part of the Si substrate is exposed.
シート部Ａ、ＢはＳｉ基板の一部でありしかもソース・
ドレイン等のデバイス形成領域内（但しチャネル部を除
く）に形成される。このシート部は２ケ所のみならず多
数形成可能である。Seat parts A and B are part of the Si substrate and are not the source.
It is formed in a device formation region such as a drain (excluding the channel part). This sheet portion can be formed not only in two locations but also in a large number of locations.
次に第２図に示すようにレジスト３を残存させた状態で
多結晶シリコンを蒸着により絶縁層と同じ厚さの約４０
００人に堆積する。Next, as shown in FIG. 2, with the resist 3 remaining, polycrystalline silicon is deposited to the same thickness as the insulating layer.
Deposited in 00 people.
次に第３Ａ図に示すように第２図に示したレジスト３と
その上の多結晶シリコン層５を除去するといわゆるリフ
トオフによりレジストを除去し平坦化を行なった後、全
面に多結晶シリコンを約４０００人の厚さに蒸着する。Next, as shown in FIG. 3A, after removing the resist 3 shown in FIG. 2 and the polycrystalline silicon layer 5 thereon, the resist is removed and planarized by so-called lift-off, and then polycrystalline silicon is applied to the entire surface. Deposited to a thickness of 4,000 people.
第３Ｂ図には第３Ａ図におけるデバイスのソース（Ｓ）
、ドレイン（Ｄ）。Figure 3B shows the source (S) of the device in Figure 3A.
, Drain (D).
ゲート（Ｇ）の各位置とシート部の位置関係を示す。The positional relationship between each position of the gate (G) and the seat portion is shown.
本実施例ではシート部Ａ、Ｂがそれぞれ第３Ｂ図のＳ、
Ｄ部に対応している。シート部は次に第４図に示すよう
にＣＷ−アルゴンレーザによりシート部Ａ、Ｂから単結
晶を成長させ第３Ａ図の多結晶シリコン層５を再結晶化
し単結晶化する。In this embodiment, the seat portions A and B are S and S in FIG. 3B, respectively.
It corresponds to part D. Next, as shown in FIG. 4, a single crystal is grown from the sheet portions A and B using a CW-argon laser, and the polycrystalline silicon layer 5 shown in FIG. 3A is recrystallized to become a single crystal.
次に０＋のイオン注入（１，１，）を４００ＫｅＶ。Next, 0+ ion implantation (1, 1,) was performed at 400 KeV.
１．５Ｘ１０”７ｃｍで選択的ニシート部上方Ｃ，Ｄに
注入し、その後、１２５０℃の温度、２時間Ｎ２熱処理
を施こし絶縁層８．９を第５図に示すように連続的に形
成しＳｏｌ （５ｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔ
ｉｎｇＳｕｂｓｔｒａｔｅ ）単結晶化の構造を得る。A layer of 1.5 x 10"7 cm was injected into the upper portions C and D of the selective sheets, and then subjected to N2 heat treatment at a temperature of 1250° C. for 2 hours to form an insulating layer 8.9 continuously as shown in FIG. Sol (5ilicon On Insulat
ingSubstrate) Obtain a single crystal structure.
その後絶縁層ＩＯを形成し素子分離を行ない、通常のＳ
ＯＩ／ＭＯＳＦＥＴの工程（Ｓ、Ｄ、Ｇの形成）を経て
第６Ａ図に示すデバイスが形成される。１０はゲート電
極である。After that, an insulating layer IO is formed to perform element isolation, and a normal S
The device shown in FIG. 6A is formed through the OI/MOSFET process (formation of S, D, and G). 10 is a gate electrode.
ｏ”−１，［、でＳｉＯ□からなる絶縁層８．９を形成
した場合その層厚は約３０００人と他のＳｉＯ□からな
る絶縁層２の領域に比較し若干薄くなるがデバイス特性
上問題はない。第６Ｂ図は第６Ａ図におけるデバイスの
ソース（Ｓ）、ドレイン（Ｄ）、ゲート（Ｇ）の各位置
とシート部の位置関係を示す。o"-1, [, when the insulating layer 8.9 made of SiO There is no problem. FIG. 6B shows the positional relationship between the source (S), drain (D), and gate (G) of the device in FIG. 6A and the seat portion.
以上説明したように本発明によればシート部が複数個デ
バイス内に形成できるのでシート部を介して多結晶シリ
コン層が容易に単結晶化し、且つリフトオフ技術を使用
しているのでシート部の凹凸もなく、その後０”−１，
１，でシート部をＳｏｌ化しているので浮遊容量も低減
化できる。再にシート部をデバイス内に形成できるので
集積度の低下も防ぐことができる。As explained above, according to the present invention, a plurality of sheet portions can be formed in a device, so that the polycrystalline silicon layer can be easily made into a single crystal through the sheet portions, and since a lift-off technique is used, the unevenness of the sheet portion can be easily formed. None, then 0”-1,
1, since the sheet portion is made into Sol, stray capacitance can also be reduced. Since the sheet portion can be formed within the device again, a decrease in the degree of integration can also be prevented.
第１図から第６Ａ図は本発明の製造工程を説明するため
の断面図であり、そのうち第３Ｂ図は第３Ａ図の模式平
面図であり、第６Ｂ図は第６Ａ図の模式平面図である。
１・・・５ｉ（１００）基板、 ２・・・絶縁層、
３・・・レジスト、 ４・・・窓、５．６・
・・多結晶シリコン層、
７・・・単結晶シリコン層、 ８．９・・・絶縁層、１
０・・・ゲート電極。
第１図
第２図
第３Ａｌ１２２！
第３８図
１・・・５ｉ（Ｚｏｏ）基板
２・・絶縁層
３・ レノスト1 to 6A are cross-sectional views for explaining the manufacturing process of the present invention, of which FIG. 3B is a schematic plan view of FIG. 3A, and FIG. 6B is a schematic plan view of FIG. 6A. be. 1... 5i (100) substrate, 2... Insulating layer,
3...Resist, 4...Window, 5.6.
... Polycrystalline silicon layer, 7... Single crystal silicon layer, 8.9... Insulating layer, 1
0...Gate electrode. Figure 1 Figure 2 Figure 3 Al122! Figure 38 1...5i (Zoo) Substrate 2... Insulating layer 3 Renost
Claims (1)
工程、 （ロ）該デバイス形成領域内でしかもチャネル領域以外
の領域にある該絶縁層（２）にレジスト（３）を用いて
単結晶成長用の窓（４）開けを行なう工程、（ハ）該レ
ジスト（３）を残存させた状態で第１の多結晶シリコン
層（５）を全露出面に形成する工程、（ニ）リフトオフ
技術により前記残存レジスト（３）及び該レジスト上の
多結晶シリコン層を除去した後全面に第２の多結晶シリ
コン層（６）を形成する工程、 （ホ）レーザアニール処理により前記第１の多結晶シリ
コン層全体を単結晶化する工程、 （ヘ）前記シート部に選択的にＯ＾＋イオンを注入し、
アニール処理を行なう工程、 を含む半導体装置の製造方法。[Claims] 1. The following steps (a) to (f): (a) forming an insulating layer on the single crystal silicon substrate (1); (b) forming an insulating layer within the device formation region and other than the channel region; (c) opening a window (4) for single crystal growth in the insulating layer (2) in the region using a resist (3); (c) opening a window (4) for single crystal growth with the resist (3) remaining; Step (d) of forming a crystalline silicon layer (5) on the entire exposed surface, (d) removing the remaining resist (3) and the polycrystalline silicon layer on the resist by a lift-off technique, and then forming a second polycrystalline silicon layer (2) on the entire surface; (e) forming the entire first polycrystalline silicon layer into a single crystal by laser annealing; (f) selectively implanting O^+ ions into the sheet portion;
A method for manufacturing a semiconductor device, including the step of performing an annealing treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62285438A JPH01128574A (en) | 1987-11-13 | 1987-11-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62285438A JPH01128574A (en) | 1987-11-13 | 1987-11-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01128574A true JPH01128574A (en) | 1989-05-22 |
Family
ID=17691524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62285438A Pending JPH01128574A (en) | 1987-11-13 | 1987-11-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01128574A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6074928A (en) * | 1997-02-12 | 2000-06-13 | Nec Corporation | Method of fabricating SOI substrate |
-
1987
- 1987-11-13 JP JP62285438A patent/JPH01128574A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6074928A (en) * | 1997-02-12 | 2000-06-13 | Nec Corporation | Method of fabricating SOI substrate |
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