JPS6282828A - Method and device for removing inter-code interference due to feedback of decision - Google Patents

Abstract

PURPOSE:To simplify control, to reduce the size of hardware and to remove an interference in a symbol waveform by forming subtractors, an adder, a deciding unit, a pattern checking circuit, and plural adaptive filters. CONSTITUTION:A receiving signal including an inter-code interference is supplied from a transmission line to an input terminal 1 and inputted to a subtractor 2 and a difference signal (receiving signal including a residual inter-code interference) obtained by subtracting a false inter-code interference outputted from the adder 19 from the receiving signal is outputted from the subtractor 2. The difference signal is supplied to the deciding unit 3, the pattern checking circuit 12, the adaptive filter, etc., to find out the sum or difference between the current sample value and a sample value obtained before iTsec and to extract the residual inter-code interference. A factor is updated by using the sum or difference as an error signal only when the residual inter-code interference is correctly extracted. Consequently, the control can be simplified, the size of the hardware can be reduced and the interference in a symbol waveform can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an intersymbol interference removal method and apparatus using decision feedback for removing intersymbol interference that occurs during waveform transmission.

(Prior Art) Decision feedback is known as a known technique for removing intersymbol interference that occurs during waveform transmission. C.O.
MMtJNICATIONS) Volume 32 No. 3 1 19
1984.

Pages 258-266. ) FIG. 8 shows a conventional example of a decision feedback type equalizer.

Here, the circuit shown in FIG. 8 is connected to the transmitting side via a transmission path. Here, for simplicity, explanation will be given assuming baseband transmission.

In FIG. 8, a received code including intersymbol interference is supplied from a transmission path to an input terminal 1, and is input to a subtracter 2.

The subtracter 2 generates a difference signal obtained by subtracting the number-like intersymbol interference generated by the adaptive filter 5 from the received signal supplied to the input terminal 1 (=received signal including residual intersymbol interference, [
Residual intersymbol interference]=[intersymbol interference]−[pseudo intersymbol interference]) is obtained and supplied to the determiner 3 and the subtractor 6. The determiner 3 determines the received signal data from the output of the subtracter 2,
The judgment result is sent to the output terminal 4 and the automatic gain FA rectifier (hereinafter referred to as
(abbreviated as AGC) 7 and an adaptive filter 5. The pseudo intersymbol interference adaptively generated by the adaptive filter 5 is supplied as one input to the reducer 2 . The output signal of the determiner 3 supplied to A, GC 7 is multiplied by 1 and input to the subtracter 6. Here, r is a positive number. The signal supplied from the AGC 7 to the subtracter 6 is subtracted w-g from the difference signal supplied to the subtracter 6, and is fed back to the AGC 7 as a control signal. The AGC 7 uses the signal fed back from the subtracter 6 to correct r so that the output from the subtracter 6 is equal to the residual intersymbol interference.

That is, the closed loop circuit consisting of the subtracter 6 and the AGC 7 operates to extract only the residual intersymbol interference in the difference signal that is the output of the subtracter 2. This is realized by adaptively determining the gain of the output signal of the AGC 7 by correlating the output signal of the subtracter 6 and the output signal of the determiner 3 in the AGC 7. The residual intersymbol interference that is the output of the subtracter 6 is also supplied to the adaptive filter 5, and the closed loop circuit consisting of the 0 subtracter 2, the determiner 3, and the adaptive filter 5 used for updating the coefficients is connected to the input terminal IK. It operates to remove intersymbol interference in the received signal.

(Problems to be Solved by the Invention) In order for the adaptive filter 5 to perform a 14 response operation, it is necessary to supply the adaptive filter 5 with -1EL<residual intersymbol interference. However, subtractor 2
Since the difference (i) which is the output signal of ability will be lost0
In the past, as shown in FIG. 8, a subtracter 5. AG
A method has been used in which the adaptive operation of the adaptive filter 5 is guaranteed by adding C7 and subtracting signals other than pseudo residual intersymbol interference from the difference signal that is the output signal of the subtracter 2. However, in the conventional control method, the AGC 7 is required, and in order to obtain a sufficient degree of intersymbol interference suppression, it is necessary to maintain the received signal, which does not include intersymbol interference, supplied from the AGC 7 to the subtracter 6 at a desired level. This method has the drawback of requiring complicated control and increasing the size of the software. Furthermore, although the conventional decision-feedback type geometric ratio can remove inter-symbol interference caused by the sequence of past transmitted symbol waveforms, it is impossible to remove interference within symbol waveforms. Another object of the present invention is to provide a method and apparatus for eliminating intersymbol interference using decision feedback, which is simple and has a small hardware scale. An object of the present invention is to provide a method and apparatus for intersymbol interference cancellation using decision feedback, which can eliminate not only intersymbol interference but also interference within symbol waveforms.

(Means for solving the problem) According to the present invention, when removing intersymbol interference that occurs during waveform transmission, a signal is obtained by subtracting pseudo intersymbol interference from a received signal containing intersymbol interference. After that, residual intersymbol interference is obtained by adding or subtracting the nuclear difference signal and a delayed signal that delays the difference signal, and either the polarity of the residual intersymbol interference or the polarity of the difference signal is sampled. When the polarity of the residual intersymbol interference is selected based on the phase and the error signal selected based on the demodulated data series obtained by demodulating the difference signal and the demodulated data series, the polarity of the demodulated data series is selected. a first adaptive filter that updates coefficients only when a specific pattern is detected; and a second adaptive filter that receives the polarity of the difference signal and updates coefficients only when the demodulated data series reaches a specific value. There is obtained an intersymbol interference removal method using decision feedback, characterized in that the pseudo intersymbol interference is generated by adding the outputs of the first and second adaptive filters.

Further, according to the present invention, a subtracter for obtaining a difference between a received signal and the first pseudo intersymbol interference when removing intersymbol interference that occurs during waveform transmission; a first adaptive filter that receives the demodulated data and the first error signal supplied from the determiner and adaptively generates a second pseudo intersymbol interference; a plurality of cascaded sample-and-hold circuits for sampling and holding the output of the subtracter;
an arithmetic unit for obtaining the sum or difference between the output of the subtracter and the output of the cascaded sample-and-hold circuit; a first polarity detection circuit for detecting the polarity of the output signal of the arithmetic unit; a first selector for selecting one of the outputs of the polarity detection circuit; a pattern check circuit for receiving the demodulated data and generating a signal for controlling the first selector; a second polarity detection circuit for detecting polarity; and a second adaptive circuit receiving the output of the second polarity detection circuit and the second error signal to adaptively generate a third pseudo intersymbol interference. a filter; an adder that adds the second pseudo intersymbol interference and the third pseudo intersymbol interference to generate the first pseudo intersymbol interference; and the second pseudo intersymbol interference.
a second selector that selects either the output of the polarity detection circuit or zero based on the demodulation data; and a second selector that selects either the output of the first selector or the output of the second polarity detection circuit based on the demodulation data. a third selector that selects one of the output of the second polarity detection circuit, the output of the first selector, and the output of the third selector based on the phase of the received signal waveform. The outputs of the first switch and the second polarity detection circuit are distributed to the first switch, the second adaptive filter, or the second and third selectors based on the phase of the received 1g waveform. a second switch, the first adaptive switch uses the output of the first switch as the first error signal;
There is obtained an intersymbol interference removal device using decision feedback, characterized in that the output of the second selector is fed back to the second adaptive filter as the second error signal.

(Function) The present invention differs from the conventional method of multiplying the output of the determiner by a constant to generate a received signal that does not include residual intersymbol interference, and subtracting it from the difference signal. The system was designed so that residual intersymbol interference can be extracted accurately with a certain probability determined by the transmission path code. That is, according to the characteristics of the received signal eye pattern of the transmission line code including the binary code system, the current sample value and iT seconds (i is a positive integer, T
(data period) The minimum probability that the previous sample values are approximately the same value or that the respective absolute values are approximately the same value with opposite polarity takes a certain positive value that is not zero. Therefore, by calculating the sum or difference between the current sample value and the sample value iT seconds ago for the difference signal (=received signal containing residual intersymbol interference), the residual intersymbol interference component can be calculated with a certain positive probability that is not zero. can only be extracted. Therefore, by using the sum or difference as an error signal and updating the coefficients only when the residual intersymbol interference is correctly extracted, the adaptive operation of the adaptive filter is guaranteed. Furthermore, the present invention is designed to be able to eliminate interference within a symbol waveform, which was not possible with conventional methods, by providing a one-tap adaptive filter for eliminating interference within the symbol waveform. As a result, it is more resistant to clock jitter than conventional devices, and performance can be improved.

(Example) The present invention will be described in detail in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, a received signal containing intersymbol interference is supplied from a transmission path to an input terminal l, and is supplied to a subtracter 2. First, transmission line codes will be explained.

FIG. 2 shows the transmitted symbol waveform and state transition of an MSK (minimum shift keying) code as an example of a transmission line code. As shown in Figure 2, in the MSK code, four types of transmission symbol waveforms are prepared: 0,
2-mode and @1 mode, which have opposite polarities, are determined by the mode one symbol before.

This MSK code has a property that the polarity always inverts at the boundary of the transmitted symbol waveform. Note that in the MSK code, the positive and negative values are balanced within one symbol for data @1'', but the positive and negative values are not balanced for data ``0''. However, the situation in Figure 2 As is clear from the direction of the thick arrow indicating the transition, if there is an even number of 10'' in one continuous data series, the positive and negative values are balanced υ, and the DC component can be almost ignored. The transmission path code shown in FIG. 2 is transmitted through the transmission path and is input to the input terminal 1 of FIG. 1 after receiving intersymbol interference.

The difference signal obtained by subtracting the pseudo intersymbol interference which is the output of the adder 19 in the subtracter 2 (=received signal containing residual intersymbol interference) is sent to the determiner 3 and the temp/I/-hold circuit 8+ s 8t W −* 8p (p=iXR)
A 0 determiner 3 supplied to an adder 9 and a block consisting of a cascade connection of 12, selectors 14 and 17, and the adaptive filter 5. Adaptive filter 5, adder 19, subtractor 2% sample/hold circuit 81t8! t..., 8. (adder 9, polarity detection circuit 10, selector 1)
, the closed loop circuit consisting of the switch 13 is an adaptive
In order to realize the adaptive operation of filter 5, pattern check circuit 12 controls the closed loop circuit to selectively update coefficients. The selector 1) selects either the output of the pattern check circuit 12 or zero based on the signal from the pattern check circuit 12 and supplies it to the switch 13. The switch 13 selects the output of the selector 1), the output of the selector 14, or the output of the switch 16 based on the sampling phase, and selects the output of the selector 1), the output of the selector 14, or the output of the switch 16.
Supplied to filter 5. Next, the relationship between the output of the adder 9 and the residual intersymbol interference in the difference signal that is the output of the subtracter 2 will be explained in detail.

FIG. 3 shows an example of a received signal eye pattern when the transmission line code shown in FIG. 2 is adopted. As shown in the figure, the 5 received signal eye pattern has high frequency components removed and becomes rounded. Originally, the received 1g signal eye pattern contains intersymbol interference components, but the eye pattern shown at first to simplify the explanation is the case when waveform equalization is ideally performed, and the intersymbol interference component is included in the received 1g signal eye pattern. It shall not contain any interfering components.

According to the characteristics of the received signal eye pattern shown in FIG. 3, when the current received signal waveform and the data of the received signal waveform i symbols (i is a positive integer) before match and the modes are different,
The received signal can be canceled by adding the received signal waveform i symbols before to the current received signal waveform.
Therefore, when MSK is used as a transmission line code, cancellation of received signals is performed with a probability of 1/4. Now, considering a non-ideal case, the received signal contains 1 residual inter-symbol interference component.If we consider 0 residual inter-symbol interference components, the current residual inter-symbol interference component and the residual inter-symbol interference before i symbol The residual intersymbol interference component before the i symbol can be regarded as random noise. The amplitude distribution of the residual intersymbol interference component before the i symbol is symmetrical, and the amplitude d is 1d1<δ (however, O≦δ
) is not zero, but takes a certain positive value. Therefore,
It can be seen that the probability that only the residual intersymbol interference component is extracted as the output signal of the adder 9 is a non-zero positive value.In addition, in general, the magnitude of the residual intersymbol interference component is sufficiently small compared to the received signal. Therefore, the waveform shown in FIG. 3 can be regarded as the received signal waveform even if it is not ideal. Therefore, if the adaptive filter 5 is controlled using the output of the adder 9, then The received signal that interferes with the adaptive operation of the adaptive middle filter 5 is canceled out,
Adaptive operation of the adaptive filter 5 is guaranteed. Note that if the conditions that the current received signal waveform and the data of the received signal waveform i symbols (i is a positive integer) before match and the modes are different are not satisfied, the control of the adaptive filter 5 in FIG. 1 is not correct. Not done. Therefore, in order to correctly control the adaptive filter 5, it is necessary to check the data and mode of the received signal waveform, and to stop updating the coefficients of the adaptive filter 5 when the received signals are not canceled out. Control of this coefficient update is realized by the pattern check circuit 12 and selector 1).
The purpose is to detect that the received signal waveform data T seconds ago are equal and have different modes, and to stop updating the coefficients of the adaptive filter 5 in other cases, and can be realized by the circuit shown in FIG.

The input signal 51 in FIG. 4 is equal to the data signal which is the output signal of the determiner 3 in FIG. 1, and the input signal 52 is equal to the mode signal. In FIG. The path connecting the determiner 3 and the adaptive filter 5 is shown as one line, but if a code is used for M8, two paths corresponding to the data signal and the mode signal are all shown. Slow FA element 53 giving a delay of iT seconds
and negative exclusive OR circuit (XNOR) 55,
It is checked whether the data signals of the current signal and the signal iT seconds ago match. This is realized by calculating the negative exclusive OR of the input signal 51 and the value of the input signal 51 delayed iT seconds by the delay element 53 using the XN0R 55. X
The output of N0R55 becomes one input of an AND circuit (AND) 59. The input signal 52 and the delay element 56 are the same
9, and the output is A.
This is the other input of ND59. AND59 ANDs the coincidence output of the data signal and the mismatch output of the mode signal to produce an output signal 60. Output signal 60 is equal to the signal provided to selector IIK from pattern check circuit 12 of FIG. Note that a delay element 53 that provides a delay of iT
．． 56 is a flip-flop i 1[! This is achieved by connecting them in series.

The selector 1) receives a control signal from the pattern check circuit 12, selects the output of the υ adder 9 or zero according to the control signal, and supplies the selected output to the adaptive filter 5. Selector 1) sends the output signal of adder 9 to adaptive filter 5.
As already explained, the pattern check circuit detects that the data of the current received signal waveform and the received signal waveform iT seconds ago match and the modes are different. Selector 1) and pattern φ check circuit 12
If only the residual inter-symbol interference is extracted accurately, then the residual inter-symbol interference is selected, and in other cases, it is zero (selector 1).
You get the output of

On the other hand, the difference signal which is the output of the subtracter 2 is sent to the polarity determination circuit 15.
After the polarity of the difference signal is detected, it becomes an input to the switch 16. The switch 16 has four output contacts, and every T7'R seconds (assuming R is a positive integer and 几=4), from the first output contact to the fourth output contact as shown in FIG. Switch in order in the direction of the arrow to output O as the first, second, third, and fourth output contacts in order from the left in the same figure,
Repeat this action every second. The sampling phase of operation of switch 16 is shown in FIG. *
tl, 'tt t, respectively, are switch 1 in Figure 1.
6 corresponds to the sampling phase of the first, second, third, and fourth output contacts. The output of the third output contact of switch 16 is provided as one of the inputs of selector 14. Still, as the other input of selector 14, selector 1)
output is supplied. On the other hand, the data signal which is the judgment result of the judge 30 is inputted to the selector 14 as a control signal, and when the data signal is @1), the output of the third output contact of the switch 16 is selected and output. However, when the data signal is ``0'', the output of selector 1) is selected and output. That is, as is clear from the output waveform of FIG. 3, when the data signal is @1), the switch 16 shown in FIG. 1 has a zero crossing point at the center of the symbol.
The output of the third output contact of the selector 1) becomes the residual intersymbol interference component, whereas when the data signal is 10", there is no zero crossing point at the center of the symbol, so the output of selector 1) becomes the residual intersymbol interference component. Therefore, the output of the selector 14 is.

It is applied to the third input contact of the switch 13 as the residual intersymbol interference component of the sampling phase t. switch 13
is a switch having four input contacts, and in synchronization with the switch 16, from the first input contact to the fourth input contact every 1 second (assuming R=4 here). The inputs are sequentially switched in the direction of the arrow in FIG. In order from the left in the figure, the input contacts are 1st, @2, 3rd, and 4th, and 1
Repeat this action every second. "Or'l" shown in Figure 3
pF.

The first input contact of switch 13 has a first output of switch 14, with t corresponding to the sampling phase of the first, second, third and fourth input contacts, respectively, by the switch of FIG. The output of the contact is supplied to the second and fourth input contacts, and the output of the selector 14 is supplied to the third input contact, as described above. As shown in FIG. 3, at one sampling phase t1 and t, no zero crossing point occurs, so the residual intersymbol interference component obtained as the output of selector 1) in FIG. Selectively update tap coefficients. Selecting zero in selector 1) means that the tap coefficients are not updated, and corresponds to the case where no residual intersymbol interference component is obtained. In addition, in sampling phase 1), data signals @O" and @1"
The residual intersymbol interference component corresponding to is obtained at the output of the selector 14 and supplied to the third input contact of the switch 13.

Therefore, as the output of the switch 13, the residual intersymbol interference component necessary for updating the tap coefficients is obtained at each sampling phase and is supplied to the adaptive filter 5. In the above description, R=4, but it is clear that R may be any integer greater than or equal to 2. Next, the adaptive number filter 5 will be explained in detail.

FIG. 5 shows a detailed block diagram of the adaptive filter 5 of FIG. 1. Input signals 106 and 106' in FIG. 5 correspond to the data signal and mode signal, respectively, which are the outputs of the determiner 3 in FIG. Further, the input signal 107 and the output signal 108 in FIG. 5 correspond to the output signal of the switch 13 and the output signal of the adaptive filter 5 in FIG. 1, respectively. Input pin number 106, delay element 1001, multiplier 1010.101
□,..., 101,1 and coefficient generator 102o,
102□, ..., 102B-0. The input signal 106 is also supplied to 100 delay elements and coefficient generators 102op1021p', . . . , 102R-0. Delay element 100 providing a delay of T seconds. , 100□
,...

100N/R-1 and 100;, 1004.・、I
Cl0IN/R- are connected in this order, and each can be realized by a flip-flop. Here, the number of taps N and the interpolation constant 8 are positive integers, and R is N
0 is also a divisor of . The data period of input signals 106 and 106' is T seconds. Delay element 100 * (1=1
@2 @...

The outputs of N/R-1) are outputted to multipliers 101j and 10, respectively.
1. +1°..., 101J+R-1 and coefficient generator 1
02j, 102j and 1. ....

102,+,1. In addition, the delay element 1001
(i=1.2..., N/R-1) are output from the coefficient generator 102. ．． 102. +0. ..., 10
2j+, 1 is supplied J. However, 0 multiplier 1 where j := i X R
01. .

101, +n, ..., +NR to 101 (k=o,
1. -, R-1), the coefficient generator 10
2kp 102k”...

102 is multiplied by each coefficient which is the output of +N-8 and the input mode signal (+1 or -1), each multiplication result is all sent to the adder 103. 'Ic is input and added. The outputs of the R adders 1030910"1'..., 103R-1 become input contacts of the switch 104. Switch 10
A multi-contact switch with a period of 4 T seconds, R adders 103°, 1031. -# The output of 103B-1 is selected and outputted every i'jbVc ton seconds, and is used as the output signal 108. Therefore, the output signal 108 is pseudo intersymbol interference caused by the past transmission data series, and T/R
Generated every second. On the other hand, a switch 105 that operates in synchronization with the switch 104 has input and output reversed to that of the switch 104.

That is, the switch 105 functions to distribute the input signal 107 to R contacts in JI numbers every T/second. Each contact output of the switch 105 is connected to the switch 10 that operates synchronously.
It is supplied to the coefficient generator present in the signal path input to the contact corresponding to No. 4. Next, the coefficient generation circuit will be explained in detail.

FIG. 6 shows the coefficient generator 102 of FIG. 5! ! (l=0, 1°..., N-1).

The input signal 200 in FIG. 6 is the input signal 106 in FIG. 5 or the delay elements 100□, 100□, ... p 100N/l
-1 (corresponds to the Q output signal. Similarly, the input signal 200' in FIG. 6) and the input signal 106' in FIG. It corresponds to the output signal. In addition, the input signal 20 in FIG.
1 corresponds to the contact output of the switch 105 in FIG. Furthermore, the output signal 209 in FIG. 6 corresponds to the output of the coefficient generator 102 in FIG.
In the figure, a data signal 200 indicating @0'' or @1# is supplied as a control signal to each of the selectors 204, 205, and 208.
The mode signal 200' that takes 0'' or @1'' is sent to the multiplier 20.
2 inputs. On the other hand, multiplier 202
In the 0 multiplier 202, which is supplied with an error signal 201 consisting only of residual intersymbol interference components as the other input, the mode signal 200' is multiplied by the error signal 201, and the multiplication result is sent to the adder 203. 0, where delay elements 206 and 207 providing a delay of T seconds are applied as one input of data signal 200 to 10# and 1)'' of data signal 200, respectively.
The outputs thereof can both be supplied as inputs to the selector 208.

On the other hand, the data signal 200 is input to the selector 208 as a control signal, and the data signal 200 is @0''.
When the data signal 200 is "wl", the coefficient corresponding to the output of the delay element 206 "0" is selected and output, and when the data signal 200 is "wl", the coefficient corresponding to the output "1" of the delay element 207 is selected and output. In addition, the coefficient 209 is fed back to the adder 203, and after being added with the output signal of the multiplier 202, the coefficient 209 is input to the selectors 204 and 205. Element 206
The outputs of and 207 are also supplied as inputs to selectors 204 and 205, respectively. Furthermore, selector 204
and 205 are supplied to delay elements 206 and 207, respectively. Therefore, the operations of the selectors 204, 205, and 208 will be explained.

If the data signal 200 is @0'', the selector 208
Select and output as coefficient 209. At this time, the coefficient 2
09 is input to the adder 203 and then the selector 204
is fed back to the delay element 206 via the data "0", and the coefficient corresponding to data "0" is updated. On the other hand, since the selector 205 selects the output of the delay element 207 and supplies it again to the delay element 207, the coefficient corresponding to data 1)' is not updated. Contrary to this case,
If the data signal 200 is 1)'', the selector 208
is the coefficient corresponding to the data ``1'' of the delay element 207
is selected and output as a coefficient 209. At this time, after the coefficient 209 is input to the adder 203, it is fed back to the delay element 207 via the selector 205, and the data @1
On the other hand, the selector 204 selects the output of the delay element 206 and supplies it again to the delay element 206, so the coefficient corresponding to the data @0'' is not updated. Not possible. According to the principle explained above, the coefficients to be used in the calculation of the adaptive filter are selected in accordance with the value 10' or ``1# of the data signal 200, and the coefficients that have been used are updated. By retaining the original values for unused coefficients, the coefficients of the adaptive filter can be obtained adaptively. Only the residual intersymbol interference is extracted from the output of the adder 9 in FIG. If not, the coefficients of the adaptive filter 5 are not updated and the error signal 201 becomes zero.At this time, as is clear from FIG. Convergence is guaranteed.Pseudo intersymbol interference caused by the past data sequence generated by the adaptive fill 5 is supplied to the subtracter 2 via the adder 19, and the code supplied from the input terminal 1 is Interference cancellation within the zero-order lower symbol waveform that is subtracted from the received signal including inter-interference interference will be explained.

The polarity of the difference signal that is the output of the subtracter 2 is input to the adaptive filter 18 via the polarity determination circuit 15 and the second output terminal of the switch 16 at the sampling phase t1. The polarity of the difference signal of the sampling phase t1 is the third
On the other hand, the polarity of the difference signal which is the output of the subtracter 2 is sent to the selector 17 via the polarity judgment circuit 15 and the switch 16. is input at sampling phase t,. Also, selector 1
Zero is also input to 7, and using the judgment result that is the output of judge 3, when the data signal is ``0'', zero is set to 1.
1) When 1, the residual intersymbol interference component appearing at the third output terminal of the switch 16 is selected and output, and is supplied to the adaptive filter 18. The selector 17 distinguishes that the symbol waveform representing data "0" at sampling phase t and VC does not have a zero crossing point, but always has data @1. When the data of the output signal is "1", the polarity of the residual intersymbol interference component is supplied to the adaptive filter 18, and when the data is "0", the polarity of the residual intersymbol interference component is supplied to the adaptive filter 18.
Coefficients are selectively updated only when the value is 1''.

Of the displacement from zero in the sampling phase t.

The component due to interference in the symbol waveform is the pseudo intersymbol interference generated by the adaptive filter 18.
The signal is supplied to the subtracter 2 via the adder 19, and is removed by subtracting it from the received signal containing the intersymbol interference. Next, the adaptive filter 18 will be explained in detail.

FIG. 7 is a detailed block diagram of the adaptive filter 18 shown in FIG.
01 are the output signal of the second output contact of the switch 16 in FIG. The corresponding error signal is Also, the output signal 306 of FIG. 7, corresponding to the output signal of the adaptive filter 18 of FIG. 1, is pseudo intersymbol interference due to a drop in the symbol waveform. In FIG. 7, the polarity of the difference signal 300 is provided to multipliers 302 and 305. Delay element 304, which provides a one second delay, is a coefficient memory whose output is fed to multiplier 305 to generate pseudo intersymbol interference 306. The output of delay element 304 is also output to adder 303
The output of the multiplier 302 which multiplies the polarity 300 of the difference signal and the error signal is supplied to the adder 303. When the error signal 301 is zero, the output of the multiplier 302 is zero, so the coefficients do not change, and selective updating of the coefficients is performed. In this way, the pseudo intersymbol interference at the zero crossing at the center of the symbol waveform appears at the output of the adaptive filter 18, and after being added to the pseudo intersymbol interference generated by the adaptive filter 5 in the m-counter 19, , are supplied to the subtractor 2.

In Fig. 1, only the residual intersymbol interference is extracted using the delay element and the subtractor 9, but as is clear from the eye pattern in Fig. 3, the same effect can be obtained even if the adder 9 is replaced with a subtracter. is obtained. At this time, in place of the XO circuit 58 that detects the mismatch of the mode signals in the circuit shown in FIG. In Figure 1, the sample
Hold circuit 81p82t..., 8. It was assumed that the time required for sampling is negligible, but if this assumption does not hold, the number of sample-and-hold circuits will be
It is sufficient to prepare T/(T-Rδ)+13 or more.

Here, δ is the time required for sampling by the sample-and-hold circuit, [X] is the largest integer that does not exceed X, and p = i
It is XR. The sampling period of each sample-and-hold circuit is always equal. Now, the phases of adjacent sample-and-hold circuits are shifted from each other by (T/R-δ). At this time, one sample-and-hold circuit holds the sample value for (T/R-δ) seconds, which is the time δ required for sampling. For example, i=1.几=4
．． When δ=T/32, the number of sample-and-hold circuits needs to be five or more, and when five sample-and-hold circuits are connected in series, the total hold time is 35
It becomes T/32. This is the maximum hold time that can be achieved by connecting five sample and hold circuits in series. In order to make the entire hold time T, the sample phases of adjacent sample write hold circuits may be sequentially shifted by T15. Furthermore, even if the sample phases of the four sample-and-hold circuits are sequentially shifted by 7T/32, and the remaining one is shifted by 4T/32 from the sample phase of the previous sample-and-hold circuit, the overall hold time can be reduced to T. can.

In this way, by appropriately shifting the sample phases of adjacent sample-and-hold circuits, the overall hold time can be reduced to T. Similarly, for any δ smaller than T/D, a sufficient number of samples
Any desired hold time can be obtained by connecting hold circuits in series and selecting the sample phase appropriately. Therefore, even if the time required for sampling cannot be ignored, T
Any hold time that is an integer multiple of can be obtained.

The present invention has been described above in detail based on examples. In the explanation so far, the sample and hold circuit 8198□...
・The delay amount of a block consisting of 8p cascade connections was assumed to be 1T seconds (i is a positive integer), but it goes without saying that in practice, it is sufficient if it is around iT seconds. Although the present invention has been described in detail using a code as an example, it is also possible to use, for example, a bi-phase code as the transmission line code. When a bi-phase code is used, the received signal waveform shown in Figure 3 is shifted by T/2 seconds, so the pattern check method must be unique to the bi-phase code. It won't happen. If the pattern check circuit 12 is configured as an ethical circuit that outputs @1 only when it detects a combination of waveforms that cancel out the received signal waveforms, it can be used as a pattern check circuit for MSK codes as shown in FIG. In the case of vertical and bi-phase codes, the input signal of the pattern check circuit is the data signal. In the case of zero-by-phase codes, the selector 14 control signals are different from the MSK code.

That is, 1. in FIG. The selector 14 selects the output signal depending on whether the received signal takes a value of zero at the sample point of , but in the case of a bi-phase code, t is the boundary of the symbol waveform, It is necessary to use a circuit for controlling the selector 14 tft31J in accordance with the waveform. Considering transmission line codes other than these codes in the same way, if the received signal pattern in which the received signal waveform cancels out is detected and the coefficient update of the adaptive filter 5 is controlled, residual intersymbol interference can be accurately eliminated with a certain probability. It is clear that it can be taken out.

(Effects of the Invention) As described in detail above, according to the present invention, the difference signal is determined by the value of the current value and i T seconds (where i is a positive integer and T is the data period) 1) 1. By taking the sum or difference of , the residual intersymbol interference component contained in the received signal can be accurately extracted with a probability of a certain positive value that is not zero. Therefore, by using the above sum or difference and further detecting a continuous pattern of the received signal waveform such that the residual intersymbol interference component can be extracted accurately, the sum or difference and the difference signal are calculated in accordance with the sampling phase. By controlling the adaptive filter by updating coefficients while making selections, adaptive operation is guaranteed, and an intersymbol interference removal method using decision feedback that does not require complicated control, is simple, and has small hardware scale can be provided. Also,
According to the present invention, it is possible to match the zero crossing point of a received signal with a sample point and at the same time eliminate not only intersymbol interference caused by a sequence of past transmitted symbol waveforms, but also interference within symbol waveforms. It has the advantage that the judgment timing phase can always be optimally maintained regardless of the distance, and is resistant to clock jitter.

[Brief explanation of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 4 is a block diagram showing a pattern check circuit for MsK codes, and FIG. 5 is a block diagram showing an example of the adaptive filter 5 in FIG. 1. 6 is a block diagram showing details of the coefficient generation circuit, FIG. 7 is a block diagram showing details of the adaptive filter 18 of FIG. 1, and FIG. 8 is a block diagram showing details of the coefficient generation circuit. FIG. 2 is a block diagram showing a conventional example. In the figure, 1...input terminal, 2...subtractor, 3...
... Judgment device, 4... Output terminal, 5.18... Adaptive output, f filter, 8. ．． 8□..., 8. ...Sample/hold circuit% 9,19...addition=:F,
10. 15...Polarity detection circuit, 1), 14.1
7 represents a selector, 12 represents a pattern check circuit, and 13.16 represents a switch, respectively. \--1o 2 Figure 71-3 Figure 6 Figure 77 Figure

Claims (2)

[Claims] (1) When removing intersymbol interference that occurs during waveform transmission, after subtracting pseudo intersymbol interference from the received signal containing intersymbol interference to obtain a difference signal, delay the difference signal and the difference signal. A demodulated data sequence obtained by adding or subtracting the delayed signal to obtain residual inter-symbol interference, and demodulating the difference signal using either the polarity of the residual inter-symbol interference or the polarity of the difference symbol as a sampling phase. a first step that receives an error signal selected based on the selected demodulated data sequence and the demodulated data sequence, and updates coefficients only when a specific pattern of the demodulated data sequence is detected when the polarity of the residual intersymbol interference is selected; an adaptive filter, and in response to the polarity of the difference signal, the demodulated data sequence comprises at least a specific value filter;
An intersymbol interference removal method using decision feedback, characterized in that the pseudo intersymbol interference is generated by adding the outputs of the first and second adaptive filters. (2) a subtracter for obtaining the difference between the received signal and the first pseudo intersymbol interference when removing intersymbol interference that occurs during waveform transmission; and a determiner that receives the received signal and generates demodulated data. , a first adaptive filter for receiving the demodulated data and the first error signal supplied from the determiner and adaptively generating a second pseudo intersymbol interference; and sampling the output of the subtracter. a plurality of cascade-connected sample-and-hold circuits for holding the sample-and-hold circuit; an arithmetic unit for obtaining the sum or difference between the output of the subtracter and the output of the cascade-connected sample-and-hold circuit; a first polarity detection circuit that detects the polarity of the output signal of the device; a first selector that selects either the output of the polarity detection circuit or zero;
a pattern check circuit that receives the demodulated data and generates a signal for controlling the first selector; a second polarity detection circuit that detects the polarity of the output signal of the subtracter; and the second polarity detection circuit. a second adaptive filter for adaptively generating a third pseudo-intersymbol interference upon receiving the output of the output and the second error signal; and the second pseudo-intersymbol interference and the third pseudo-intersymbol interference. an adder that adds the signals to generate the first pseudo intersymbol interference; a second selector that selects either the output of the second polarity detection circuit or zero based on the demodulated data; a third selector that selects either the output of the first selector or the output of the second polarity detection circuit based on the demodulated data; and the output of the second polarity detection circuit or the output of the first selector. and the third
a first switch that selects one of the outputs of the selector based on the phase of the received signal waveform; and a first switch that selects the output of the second polarity detection circuit based on the phase of the received signal waveform. 2 adaptive filters or a second switch that distributes to the second and third selectors, and the output of the first switch is fed back to the first adaptive filter as the first error signal. ,
An intersymbol interference removal device using decision feedback, characterized in that an output of the second selector is fed back to the second adaptive filter as the second error signal.