JPS62207031A - Desicion feedback type equalizer - Google Patents

Abstract

PURPOSE:To obtain an equalizer with simple control and small hardware scale by adopting the constitution so that an interference between residual codes is accurately extracted at a probability decided by a transmission line code. CONSTITUTION:The pseudo inter-code interference generated by an adaptive filter 5 is fed to a subtractor 2, where a difference signal (=reception signal including code between residual codes, interference between residual code= inter-code interference -interference between pseudo codes) subtracting the pseudo code interference from the reception signal being an input signal at an input terminal l is obtained and the result is fed to a block comprising the cascade connection of sample-and-hold circuits 81, 82-8p, a deciding device 3 and a subtractor 9. A selector 10 selects an output signal of the subtractor 9 or zero by using an output signal of a pattern check circuit 11 and the result is fed to the adaptive filter filter 5. The result decided by the device 3 is fed to the adaptive filter 5 and appears at the output terminal. The adaptive filter 5 uses an output signal of the selector 10 to apply revision of coefficient.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decision feedback equalizer, and more particularly to a decision feedback equalizer used to eliminate intersymbol interference that occurs during waveform transmission.

[Conventional technology]

As a conventional technique for removing intersymbol interference that occurs during waveform transmission,
IONS ON COMMUNICATIONS)
There is a decision feedback equalizer described in Vol. 32, No. 3, 1984, pages 258-266.

FIG. 6 is a block diagram of an example of a conventional decision feedback equalizer. Here, the decision feedback type equalizer shown in FIG. 6 is connected to the transmitting side via a transmission path. In the following explanation, for the sake of simplicity, it will be assumed that baseband transmission is used.

In FIG. 6, a received signal containing intersymbol interference is supplied from a transmission path to an input terminal 1, and is input to a subtracter 2.

In the subtracter 2, the difference signal obtained by subtracting the pseudo intersymbol interference generated by the adaptive filter 5 from the received signal supplied to the input signal 1 contains the residual intersymbol interference, and the residual intersymbol interference = intersymbol interference. −Pseudo intersymbol interference) is obtained.
The signal is supplied to a determiner 3 and a subtracter 6.

A determiner 3 determines the received signal data from the output of the subtracter 2, and transmits the determination result to an output terminal 4 and an automatic gain adjuster (hereinafter referred to as AG).
(referred to as O) 7 and an adaptive filter 5.

The pseudo intersymbol interference adaptively generated by the adaptive filter 5 is supplied as one input to the subtracter 2.

The output signal of the determiner 3 supplied to the AGO 7 is multiplied by γ (γ is a positive number) and input to the subtracter 6. 0 people () C7 supplies the output signal to the subtracter 6, and the ratio signal is subtracted from the subtracter 2. AGO7 is subtracted from the difference signal supplied to AGO7 as a control signal.
will be returned to. The AGO 7 uses the control signal fed back from the subtracter 6 to modify γ so that the output of the subtracter 6 is equal to the residual intersymbol interference.

That is, the closed loop circuit consisting of the subtracter 6 and the AGO 7 operates to extract only the residual intersymbol interference in the difference signal that is the output of the subtracter 2. this is.

i5. This is achieved by adaptively determining the gain of the output signal of the AGO 7. The residual intersymbol interference, which is the output of the subtracter 6, is passed through the adaptive filter 5.
is also supplied and used for coefficient update. A closed loop circuit consisting of a subtracter 2, a determiner 3, and an adaptive filter 5 operates to remove intersymbol interference in the received signal supplied to the input terminal 1.

Next, the adaptive filter 5 will be explained.

FIG. 7 is a detailed block diagram of the adaptive filter 5 of FIG. 6.

In FIG. 17, input signals 106 and 107 correspond to the binary data series that is the output signal of the determiner 3 in FIG. 6 and the output signal of the subtractor 6, respectively. Further, in FIG. 7, the output signal 108 corresponds to the output signal of the adaptive filter 5 of FIG. 6.

Input signal 106 is input to delay element 100x*multiplier 101o
, 1011 to 10IR-1 and the coefficient generator 102o.

1021 to 102R,, -1.

Delay element 1"00x, 1002~1 giving a delay of T seconds
00N/R-t are connected in this order, and each can be realized with a clip/70 tube. Here, N and R are positive integers, and υ is a divisor of N. Further, the data period of the input signal 106 is T seconds. Delay element 10
0! II C+! The outputs of l=1.2 to l1-1) are multipliers 101j and 1013+1 to l01, respectively.
and coefficient generator] 02j, 1021+t~102 soup 1
supplied to However, h J = mXR.

Multiplier 101 x a 101 k+a~101 k+
In H-B (k=Q, 1 to about -1), each coefficient generator 102 is multiplied by each coefficient and input data that are the outputs of +R to 102 k + N-H, and then each multiplication result is are all input to the adder 103k and added.

R adders 103o.

The outputs of 1031 to 103R-t become inputs to the input contacts of switch 104.

The switch 104 is a multi-contact switch with a cycle of T seconds, and has eight adders 103o, 103z to IO3*-.
Select the outputs of 1- in this order every T/R seconds to output the output signal 1.
Outputs 08. The output signal 108 is pseudo intersymbol interference fi, pseudo intersymbol interference is generated every T/R seconds. R
is called an interpolation constant (interbolation factor), and R is usually an integer of 2 or more in order to eliminate intersymbol interference within a required signal band.

On the other hand, the switch 10 that operates in synchronization with the switch 104
5 has the input and output reversed with the switch 104. That is, the switch 105 functions to sequentially distribute the input signal 107 to R contacts every T/R seconds. Each contact output of the switch 105 is supplied to a coefficient generator present in a signal path input to the contact corresponding to the switch 104 operating synchronously.

Next, the coefficient generator will be explained.

@Figure 8 shows the coefficient generator 102/(/=0.1~N
-1) is a detailed block diagram. In FIG. 8, the input signal 200Fi or the input signal 106 in FIG. 7 or the delay element 1
It corresponds to output signals of 00r+1002 to 100N/R-1. Moreover, in FIG. 8, the input signal 201 is
This corresponds to the contact output of switch 105 in FIG. Furthermore, in FIG. 8, output signal 203 corresponds to the output of coefficient generator 1021 in FIG.

In FIG. 8, input signals 200 and 201 are input to multiplier 2.
04, and the multiplication result becomes one input of the adder 205. The output of the adder 205 is the delay element 20 of T seconds.
The coefficients are updated every T seconds by adding the correlation value of the input signals 200 and 201 supplied to the multiplier 204 to the coefficient value of one sample before. . Output signal 203 is the coefficient.

[Problem that the invention seeks to solve]

In the conventional decision feedback equalizer described above, the adaptive
In order for the filter 5 to perform an adaptive operation, the residual intersymbol interference must be correctly supplied to the adaptive filter 5. However, since the difference signal that is the output signal of subtractor 2 also contains signals other than residual intersymbol interference, subtracter 2
If we assume that the output signal of is directly supplied to the adaptive filter 5, the adaptive filter 5 will lose its adaptive ability. Therefore, conventionally, as shown in FIG. 6, a method has been used in which the adaptive operation of the adaptive filter 5 is guaranteed by adding a subtracter 6 and an AGC 7 to extract the residual intersymbol interference component. Ta. However, in the conventional control method, the AGC 7 is required, and in order to obtain a sufficient degree of intersymbol interference suppression, it is necessary to maintain the received signal, which does not include intersymbol interference, supplied from the AGC 7 to the subtracter 6 at a desired level. This method requires complicated control and has the problem of increasing the hardware scale.

SUMMARY OF THE INVENTION An object of the present invention is to provide a decision feedback equalizer that is easy to control and has a small hardware scale.

[Means for solving problems]

The decision feedback equalizer of the present invention includes a subtracter that outputs a difference signal between a received signal and pseudo intersymbol interference generated based on intersymbol interference that occurs during waveform transmission, and a subtracter that inputs the difference signal and demodulates it. a determiner that outputs data; a plurality of continuously connected sample-and-hold circuits that sample and hold the difference signal; and an operation for obtaining the sum or difference between the indecency signal and the output of the sample-and-hold circuit. a pattern check circuit that inputs the demodulated data and generates a control signal; a selector that waits for input of the control signal and selects either the output of the arithmetic unit or zero and outputs an error signal; and an adaptive filter that receives stupor data and an error signal and adaptively generates the pseudo intersymbol interference.

[Effect]

The decision feedback equalizer of the present invention multiplies the output of the decider by a constant to generate a received signal that does not contain residual intersymbol interference, and subtracts it from the difference signal. By paying attention to the characteristics, we designed the system so that residual intersymbol interference can be accurately extracted with a certain probability determined by the transmission path code.

That is, according to the characteristics of the received signal eye pattern of the transmission line code including the binary code system, the current sample value and tT seconds (i
is a positive integer) The minimum probability that the previous sample values are approximately the same value, or that the respective absolute values are approximately the same value with opposite polarity, takes a certain positive value that is not zero. Therefore, by taking the difference or sum of the current sample value and the sample value 11' seconds ago for the difference signal (=received signal containing residual intersymbol interference), it is possible to obtain the residual code with a certain positive probability that is not zero. Only the interfering components can be extracted. Therefore, by using the difference or sum as an error signal and updating the coefficients only when the residual intersymbol interference is correctly extracted, the adaptive operation of the adaptive filter is guaranteed.

〔Example〕

Next, Example 1 of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating a $1 embodiment of the present invention.

The difference between the first embodiment shown in FIG. 1 and the conventional example shown in FIG. The block consists of a subtracter 9, a selector 10, a pattern
Except for the provision of the check circuit 11, the other configurations are exactly the same as in FIG.

Before explaining these circuits, the overall configuration will be described.

In FIG. 1, a received signal input to an input terminal 1 is supplied to a subtracter 2. In subtracter 2, adaptive
The difference signal obtained by subtracting the pseudo intersymbol interference generated by the filter 5 (=received signal containing residual intersymbol interference) is sent to the determiner 3. Sample and hold circuit 81.82-8.
and a subtractor 9. The output of the determiner 3 is supplied to an output terminal 4, a pattern check circuit 1, and an adaptive filter 5.

A closed loop circuit consisting of a block consisting of the adaptive filter 5, the subtracter 2, the continuous connection of the sample and hold circuits 81, 82 to 8p, the subtracter 9, and the selector 1o realizes the M-responsive operation of the adaptive filter 5. The pattern check circuit 11 controls this closed loop circuit to selectively update coefficients.

Next, the transmission line code will be described.

FIGS. 2(a) and 2(b) are waveform diagrams for explaining transmission line codes, and show typical examples of binary codes.

Figure 2(a) shows the biphase code, Figure 2(b) shows the HM
The pulse waveforms of SK (minimum shift keying) codes are shown.

As shown in Figure 2(a), in the biphase code, °O
Assign pulse waveforms with inverted polarity to # and °1'' data. The polarity of both pulses is inverted at the center of the 1-bit width T seconds, and the positive and negative values are balanced within 1 bit. It has the characteristic of being

On the other hand, as shown in FIG. 2(b), four types of pulse waveforms are prepared for 1M8. i.e. °0″ and “
For 1# data, two types of pulse waveforms are prepared: "0# mode" and "1" mode, each with inverted polarity.

These two types of mode transitions are indicated by arrows in FIG. 2(b), and the current mode is determined by the mode one symbol before. This M8 code has a property that the polarity always inverts at the boundary of the transmitted symbol waveform.

Note that in the MSK code, the positive and negative values for "1" are balanced within one symbol, but the positive and negative values for 01 are not balanced. However, as is clear from the direction of the thick arrow indicating the mode transition in Figure 2(b), if there is an even number of "0"s in the continuous data series, the positive and negative values are balanced, and the DC component is Almost negligible.

Figures 3(a) and (b) correspond to Figures 2(a) and (), respectively.
The received signal eye when the transmission line code shown in b) is adopted.
FIG. 3 is a waveform diagram showing a pattern.

As shown in FIGS. 3(a) and (b), the received signal eye
The pattern becomes rounded as the high frequency components are removed. Originally, a received signal eye pattern includes an intersymbol interference component, but to simplify the explanation, the received signal eye pattern illustrated is ideal and does not include intersymbol interference.

Now, the received signal eye of code M8 shown in FIG. 3(b).
Pay attention to patterns. According to the characteristics of the received signal eye pattern, when the data of the current received signal waveform and the received signal waveform i symbols before match, and the modes are different, the received signal waveform i symbols before is subtracted from the current received signal waveform. The received signals can be canceled by adding or

The probability of this cancellation is determined by the transmission path code, and is 1/4 if M8 is a code.

Next, considering the case where the received signal eye pattern is not ideal, the received signal contains residual intersymbol interference components. Since the current residual intersymbol interference component and the residual intersymbol interference component i symbols before are uncorrelated, the residual intersymbol interference component i symbols before can be regarded as random noise. The amplitude distribution of the residual intersymbol interference component before the i symbol is symmetrical, and the amplitude d is ldl.
The probability that ≦ε (however, g≧0) is not zero but takes a certain positive value. Therefore, it can be seen that the probability that only accurate residual intersymbol interference is extracted from the output signal of the subtracter 9 takes a certain positive value that is not zero. Furthermore, in general, the magnitude of the residual intersymbol interference component is sufficient to J\ with respect to the received signal.

Therefore, the waveform shown in FIG. 3(b) can be regarded as the received signal waveform even if it is not ideal. Therefore, by controlling the adaptive filter 5 using the output of the subtracter 9, the received signal that interferes with the adaptive operation of the adaptive filter 5 is canceled out, and the adaptive operation is guaranteed.

Note that if the condition that the current received signal waveform matches the data and mode of the received signal waveform i symbol before is satisfied, the control of the adaptive filter 5 shown in FIG. 1 will not be performed correctly. Therefore, in order to correctly control the adaptive filter 5, it is necessary to check the data and mode of the received signal waveform and stop updating the coefficients of the adaptive filter 5 when the received signal waveforms are not canceled out. Control of this coefficient update is realized by a pattern check circuit 11 and a selector 10.

FIG. 4 is a detailed block diagram of the pattern check circuit 11 of FIG. 1.

The pattern check circuit 11 checks the current received signal waveform and i.
This is to detect that the mode is equal to the data of the received signal waveform T seconds ago, and to stop updating the coefficients of the adaptive filter 5 in other cases.

In FIG. 4, the input signal 51 is equal to the data signal of the determiner 3 of FIG. 1, and the input signal 52 is equal to the mode signal. Note that in FIG. 1, the determiner 3 and the pattern check circuit 31. The path connecting the determiner 3 and the adaptive filter 5 is shown as one line, but if a symbol is used for M8, two paths are shown corresponding to the data signal and the mode signal.

A delay circuit 53 that provides a delay of iT seconds and a negative exclusive OR circuit (hereinafter referred to as XNOR) 55 check whether the current signal and the data signal of the signal i symbols before match. This is input signal 5] and input signal 51
This is realized by calculating the negative exclusive OR of the values delayed for 11 seconds by the delay circuit 53 using the XN0R 55. XN0
The output of R55 is an AND circuit (hereinafter referred to as AND) 59
This is one of the inputs. Similarly, the input signal 52 and the i-symbol delayed value are subjected to a negative exclusive OR operation in the XNO box 58, and the output is used as the other input of the AND 59.

AND59 performs a logical product of the matching output of the data signal and the matching output of the mode signal, and outputs the result as an output signal 6o. Output signal 6
0 is a control signal supplied from the pattern check circuit 11 of FIG. 1 to the selector 1o. Note that the delay circuits 53 and 56 that provide a delay of iT seconds connect the flip-flops to i
This is achieved by connecting the two in series.

A pattern check circuit 11 with ten selectors receives a control signal, selects the output signal of the subtracter 9 or zero according to the control signal, and supplies the selected signal to the adaptive filter 5. When the selector 10 supplies the output signal of the subtracter 9 to the adaptive filter 5, it is determined that the current received signal waveform and the received signal waveform data iT seconds ago match and the modes are different, as described above. This is when the pattern check circuit 11 detects this. When the residual inter-symbol interference is accurately extracted by the selector 10 and the pattern check circuit 11, the residual inter-symbol interference is obtained at the output of the selector 10, and in other cases, zero is obtained at the output of the selector 10.

In FIG. 1, the t19 pseudo intersymbol interference generated by adaptive filter 5 is fed to subtractor 2. In FIG. Subtractor 2 generates a difference signal obtained by subtracting pseudo intersymbol interference from the received signal that is the input signal of input terminal 1 (=received signal including residual intersymbol interference, residual intersymbol interference - intersymbol interference - pseudo intersymbol interference) is obtained and supplied to the subtracter 9, which is a block consisting of the determiner 3 and the continuous connection of sample and hold circuits 81, 82 to 8P.

In the selector 10, the output signal of the subtracter 9 or zero is selected by the output signal of the pattern check circuit 1 and is determined by the zero determiner 3 which is supplied to the adaptive filter 5. appears at the output terminal 7 simultaneously. Adaptive filter 5 uses the output signal of selector 10 to update coefficients.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

The difference between the second embodiment shown in FIG. 5 and the first embodiment described above is that the subtracter 9 in FIG. 1 is replaced with an adder 12, and the other parts are completely the same. It is.

Therefore, in the second embodiment, regarding the difference signal that is the output of the subtracter 2, the sum of the current difference signal value and the difference signal value iT seconds ago appears at the output of the adder 12, and the value of this sum is will be used to control the adaptive filter 5.

At this time, the pattern check circuit 11 shown in FIG.
In place of the XN0R58, which detects coincidence of mode signals, it is necessary to use exclusive OR to detect mismatch of mode signals.

In addition, in FIG. 1, the sample and hold circuit 81+
It is assumed that the time required for sampling 82 to 8p is negligible, but if this assumption does not hold, the number of sample-and-hold circuits will be (CpT/(T-Rδ))+11
You should prepare more than one. Here, δ is the time required for sampling by the sample-and-hold circuit, the number of sample-and-hold circuits [x] is the largest integer not exceeding X, and p''IXR
It is.

The sample period of each sample and hold circuit is always T/R
are equal. Now, the phases of adjacent sample-and-hold circuits are shifted from each other by (T/R-δ). At this time,
In one sample-and-hold circuit, a sample value is held for (T/R-δ) seconds, which is the time δ required for sampling.

For example, i=1. R=4. When δ=T/32, it is sufficient to prepare five or more sample-and-hold circuits, and when five sample-and-hold circuits are connected in series,
The total hold time is 35T/32. This is the maximum hold time that can be achieved by connecting five sample and hold circuits in series.

To make the overall hold time T, the sample phases of adjacent sample-and-hold circuits can be sequentially shifted by T15, and the sample phases of the four sample-and-hold circuits can be sequentially shifted by 7T/32 to reduce the remaining sample phase. Even if one of them is shifted by 4T/32 from the sample phase of the previous stage sample/hold, the entire hold time can be set to IP. In this way, by appropriately shifting the sample phases of adjacent sample-and-hold circuits, the overall hold time can be reduced to T. Similarly, T/R
For any small δ, an arbitrary hold time can be obtained by connecting an infinitesimal number of sample/hold circuits in series and appropriately selecting the sample phase.

Therefore, even if the time required for sampling is generally not negligible, it depends on obtaining an arbitrary hold time that is an integer multiple of TO.

The above has been described in detail based on the embodiments of the present invention, but M
When the code 8 is adopted, the configuration of the adaptive filter 5 is slightly different from that shown in FIG. 7 due to two reasons: the pulse waveforms for 10' and "1" are different, and each has a 0 mode and a 1 mode. Become. That is, "0" and '
It is necessary to prepare two types of tap coefficients corresponding to the different pulse waveforms of the pulse waveforms 11 and update them individually, and it is also necessary to distinguish the coefficients based on the mode signal received from the determiner 3. Furthermore, in the explanation so far, sample and hold circuits 8s, 8z to 8. It is assumed that the delay amount of the block consisting of the continuation W sand is iT seconds, but it goes without saying that in practice, it is sufficient if it is around iT seconds.

Up to now, the present invention has been described in detail using the M8 code as an example, but the bi7 code shown in FIG. 2 (@), for example, can be used as the transmission path code.

When a bi-phase code is used, the nine waveform shown in Fig. 3(a) becomes the received polar signal waveform, so the pattern check method must be unique to the bi-7 phase code. Referring to FIG. 3(a), the pattern check circuit detects a waveform pattern of 6 symbols MkalYe in total, which is 1 symbol waveform before and after the two symbol waveforms of interest, and controls the adaptive operation of the adaptive filter 5. Must be.

Considering transmission line codes other than these codes in the same way, if the received signal pattern corresponding to Fig. 3 is detected and the coefficient update of the adaptive filter 5 is controlled, the probability of residual intersymbol interference is It is clear that it can be extracted accurately.

〔Effect of the invention〕

As explained above, according to the present invention, regarding the difference signal,
By calculating the difference or sum between the current value and the value iT seconds ago, the residual intersymbol interference component contained in the received signal can be accurately extracted with a probability of a certain positive value that is not zero. Therefore, using the above difference or sum, the adaptive filter is further controlled to detect a combination of received signal waveforms that allows the residual intersymbol interference component to be extracted accurately and to selectively update the coefficients. Therefore, adaptive behavior is guaranteed. In addition, by combining a continuously connected sample-and-hold circuit that provides an 11-second delay and an arithmetic unit, the above-mentioned adaptive operation can be guaranteed, making it simple and easy to use on a hardware scale without requiring complicated control. This has the advantage that a small decision feedback type equalizer can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
Figures (a) and (b) are waveform diagrams for explaining the transmission line code, and Figures 3 (a) and (b) are for explaining the received signal eye pattern corresponding to the transmission line code in Figure 2. 4 is a detailed block diagram of the pattern check circuit of FIG. 1, FIG. 5 is a block diagram showing the second embodiment of the present invention, and FIG. 6 is a conventional decision feedback equalizer. 7 is a detailed block diagram of the adaptive filter of FIG. 6, and FIG. 8 is a detailed block diagram of the coefficient generation circuit of FIG. 7. 1...Input terminal, 2...Subtractor, 3.
...Judgment device, 4...Output terminal, 5...
...Adaptive filter, 81182-8.・・・
...Sample and hold circuit, 9...Subtractor, 10...Selector, 11...Pattern check circuit, 12...Adder. ′-゛n゛・, Susumu Uchihara, Daigajin Patent Attorney 12. Pa); ri咥-1fB '2=Shibuno L-2t;
-jL ト”ElkoC 噌5・茅!5: Wa (1″′) 茅3 fig 茅4-father) l 圓

Claims (1)

[Claims] a subtracter that outputs a difference signal between the received signal and pseudo intersymbol interference generated based on intersymbol interference that occurs during waveform transmission; a determiner that inputs the difference signal and outputs demodulated data; and the difference signal. a plurality of continuously connected sample-and-hold circuits that sample and hold the sample-and-hold circuit; an arithmetic unit that obtains the sum or difference between the difference signal and the output of the sample-and-hold circuit; and a control unit that inputs the demodulated data. a pattern check circuit that generates a signal; a selector that outputs an error signal by selecting either the output of the arithmetic unit or zero when the control signal is input; and an adaptive circuit that inputs the demodulated data and the error signal. Adaptive code that generates the pseudo intersymbol interference
A decision feedback equalizer comprising a filter.