JPS62247633A - Method and device for elimination fo inter-code interference by decision feedback - Google Patents

Abstract

PURPOSE:To eliminate even the interference occurring within a symbol waveform by using two types of one-tap adaptive filters. CONSTITUTION:It is possible to extract only the residual inter-code interference component with a certain positive probability excepting for zero by obtaining the sum of or the difference between the present sample value and that used before MT seconds (M: an integer, T: a data period) in terms of a difference signal( received signal containing the residual inter-code interference component). Then the update of coefficients is carried out only when said interference compo nent is correctly extracted. Thus the adaptive working of an adaptive filter 25 is secured. While the interference component produced by the interference occurring within a symbol waveform is eliminated by supplying the artificial inter-code interference signals produced by an adaptive filter 18 to a subtractor 2 via adders 21 and 22 and then subtracted from the received signals undergone the inter-code interference. An adaptive filter 20 eliminates the inter-code interfer ence produced at a zero-cross point of the same symbol waveform end.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an intersymbol interference removal method and apparatus using decision feedback for removing intersymbol interference that occurs during waveform transmission.

Prior Art J A decision feedback type isolator is known as a known technique for removing intersymbol interference that occurs during waveform transmission. (IEEE TRANSACTIONS ON COMMUNICATIONS)
OMMUNIcATIONS) Volume 32 No. 3, 1984
Year, pages 258-266. ) FIG. 9 shows a conventional example of a decision feedback equalizer.

The circuit shown in FIG. 9 is connected to the transmitting side via a transmission line. For simplicity, the explanation will be based on the assumption of baseband transmission.

In FIG. 9, a received signal subjected to intersymbol interference is supplied from a transmission path to an input terminal 1, and inputted to a subtracter 2.

The subtracter 2 produces a difference signal obtained by subtracting the pseudo intersymbol interference signal generated by the adaptive filter 5 from the received signal supplied to the input terminal 1 (=received signal containing the residual intersymbol interference component, [residual intersymbol interference component ]=[Intersymbol interference component]−
[Pseudo intersymbol interference signal]) is obtained and supplied to the determiner 3 and the subtracter 6. A determiner 3 determines the received signal data from the output of the subtracter 2, and transmits the determination result to an output terminal 4, an automatic gain controller (hereinafter abbreviated as AGC) 7, and an adaptive controller.
Supplied to filter 5. The pseudo intersymbol interference signal adaptively generated by the adaptive filter 5 is supplied as one input of the subtracter 2. The output signal of the determiner 3 supplied to A G<, near is multiplied by γ and input to the subtracter 6. Here, γ is a positive number. The signal supplied from the AGC7 to the subtracter 6 is subtracted from the difference signal supplied to the subtracter 6, and is fed back to the AGC7 as a control signal. A
tH; r Near, the signal fed back from the subtracter 6 is used to correct γ so that the output of the subtracter 6 is equal to the residual intersymbol interference component. That is, subtractor 6 and A
The closed loop circuit consisting of C7 operates to extract only the residual intersymbol interference component in the difference signal that is the output of subtractor 2. This is achieved by correlating the output signal of the subtracter 6 and the output signal of the determiner 3 in the AGC 7.
This is achieved by adaptively determining the gain of the output signal of No.7. The residual intersymbol interference component, which is the output of the subtracter 6, is co-fed to the adaptive filter 5 and used for coefficient updating. Subtraction ≧ filter 2, judger 3, adaptive filter 5
The closed-loop circuit consisting of the input terminal 1 operates to eliminate intersymbol interference experienced by the received signal applied to the input terminal 1.

[Problem that the invention attempts to solve]

In order for the adaptive filter 5 to perform an adaptive operation, it is necessary to correctly supply the residual intersymbol interference component to the adaptive filter. However, since the difference signal, which is the output signal of the subtracter 2, contains signals other than the residual intersymbol interference component, assuming that the output signal of the subtracter 2 is directly supplied to the adaptive filter 5, the adaptive filter 5 The adaptive ability of the filter 5 will be lost. Therefore, conventionally, as shown in FIG. 9, subtracters 6, A (E
:t A method has been used in which the adaptive operation of the adaptive filter 5 is guaranteed by extracting the residual intersymbol interference component using C7. However, in such a control method, the AGC 7 is required, and in order to obtain a sufficient degree of intersymbol interference suppression, the subtracter 6 must be equipped with the AGC 7.
requires complex control to maintain the received signal, which is supplied from the
The drawback was that the hardware scale became larger. Furthermore, the b'C-long decision feedback type equalizer can only remove intersymbol interference caused by a sequence of past transmitted symbol waveforms, but cannot remove interference within symbol waveforms.

The purpose of the present invention is to provide simple and small hardware scale.
The object of the present invention is to provide a method and apparatus for eliminating intersymbol interference using decision feedback. Another object of the present invention is to provide an intersymbol interference cancellation method using decision feedback that is capable of removing not only intersymbol interference caused by a sequence of past transmitted symbol waveforms, but also interference within symbol waveforms. The purpose is to provide equipment.

, Means for Solving Problems] 1 According to the present invention, after obtaining a difference signal by subtracting a condensed intersymbol interference signal from a received signal subjected to intersymbol interference, the difference signal and the difference signal are Delayed signal 3 addition'! A residual inter-symbol interference component is obtained by subtracting the residual inter-symbol interference component, and a first adaptive filter converts either the polarity of the residual inter-symbol interference component or the polarity of the difference signal into the sampling phase and the difference signal. When the polarity of the residual intersymbol interference component is selected based on the demodulated data sequence and an error signal selected based on the demodulated data sequence obtained by demodulating the signal, a specific pattern of the demodulated data sequence is received. is detected, and a second adaptive filter receives the polarity of the difference signal and the polarity of the first half of the next symbol waveform predicted from the demodulated data sequence, so that the demodulated data sequence has a specific value. The coefficients are updated only when the symbol waveform of the difference signal is completely received by the third adaptive filter. 1.
Second. An intersymbol interference removal method using decision feedback is obtained, which is characterized in that the pseudo intersymbol interference signal is generated by adding the outputs of the third adaptive filter.

Further, according to the present invention, a subtracter for obtaining a difference between a received signal and a pseudo intersymbol interference signal, a first determiner that receives the output of the subtracter and produces demodulated data, and the first determiner a first adaptive filter receiving the demodulated data and a first error signal supplied from the subtracter; a plurality of cascaded sample and hold circuits for sampling and holding the output of the subtracter; an arithmetic unit for obtaining the sum or difference between the output of the subtracter and the output of the cascaded sample-and-hold circuit; a first polarity detection circuit for detecting the polarity of the output signal of the arithmetic unit; a first selector that selects either the output of the polarity detection circuit of 1 or zero; a pattern check circuit that receives the demodulated data and generates a signal that switches the first selector; and the subtracter. a second polarity detection circuit for detecting the polarity of the output signal; a first switch for distributing the output of the second polarity detection circuit based on the phase of the received signal; and a first switch for distributing the output of the second polarity detection circuit based on the phase of the received signal; a polarity prediction circuit that predicts the polarity of the first half;
a second adaptive filter receiving a prediction signal and a second error signal supplied from the polarity prediction circuit; and selecting either one contact output or zero of the first switch based on the demodulated data. a third selector that selects either the output of the first selector or the one contact output of the first switch based on the demodulated data; a second switch that selects one of the outputs of the two output contacts, the output of the first selector, and the output of the third selector based on the phase of the received signal; a second determiner that generates temporary demodulated data before completely receiving the output symbol waveform; a third adaptive filter that receives the output of the second determiner and a third error signal; 1. an adder that adds the outputs of the second and third adaptive filters to generate the pseudo intersymbol interference signal;
is fed back to the first adaptive filter as an error signal, and the output of the second selector is fed back to the second adaptive filter as the second error signal,
There can be obtained an intersymbol interference removal device using decision feedback, characterized in that one contact output of the first switch is fed back to the third adaptive filter as the third erroneous signal.

・Effect 1 Unlike the conventional method of multiplying the output of the determiner by a constant to generate a received signal that does not contain residual intersymbol interference components and subtracting the residual intersymbol interference component from the difference signal, this JFI method calculates the eye pattern of the received signal. The system was designed so that the residual intersymbol interference component can be accurately extracted with a certain probability determined by one path code. In other words, the received signal eye of the transmission line code underlying the binary code system
According to the characteristics of the pattern, if the intersymbol interference is negligible, the current sample value and the sample value MT seconds ago (M is a positive integer, T is the data period) are almost the same value, or have opposite polarities and their respective absolute values. The minimum probability that the values are almost the same takes a certain positive value that is not zero. Therefore, by taking the sum or difference between the current sample value and the sample value MT seconds ago for the difference signal (=received signal with residual inter-symbol interference components), the residual inter-symbol interference component can be calculated with a certain positive probability that is not zero. Only interference components can be extracted. Therefore, by using the sum or difference as an error signal and updating the coefficients only when the residual intersymbol interference component is correctly extracted, the adaptive operation of the adaptive filter is guaranteed. Furthermore, by providing two types of one-tap adaptive filters for eliminating interference within a symbol waveform, the present invention is configured to be able to eliminate interference within a symbol waveform, which was impossible with conventional methods. As a result, it is more resistant to clock jitter than conventional devices, and performance can be improved.

[Example] Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, a received signal subjected to intersymbol interference is supplied from a transmission path to an input terminal 1, and is supplied to a subtracter 2. First, transmission line codes will be explained.

Figure 2 shows MSK (minimum code) as an example of a transmission line code.
Shift keying) shows the symbol waveform and state transition of the code. As shown in FIG. 2, four types of symbol waveforms are prepared in the MSK code. That is, "o" and °゛1
For the data of °゛, the polarity is reversed respectively ゛°+°
Prepare two types of waveforms: '' mode and '-'' mode9
These four types of state transitions are indicated by arrows in FIG. 2, and the current mode is determined by the mode one symbol before. This MSK code has the property that the polarity always inverts at the boundary of the symbol waveform. The transmission path code shown in FIG. 2 is transmitted through the transmission path and is input to the input terminal 1 of FIG. 1 after receiving intersymbol interference.

The difference signal obtained by subtracting the pseudo intersymbol interference signal which is the output of the adder 22 in the subtracter 2 (=received signal containing residual intersymbol interference component) is sent to the determiner 3, sample and hold circuit 81, 8□.

. . , 8p (p=MR) in cascade connection, and is supplied to an adder 9, a polarity determining circuit 15, and one determining device. The determiner 3 determines the data and mode corresponding to the received symbol waveform every T seconds, and its output is sent to the output terminal 4, the pattern check circuit 12, the selectors 14 and 17, the adaptive filter 25, and the polarity. It is supplied to the prediction circuit 23. Adaptive filter 2
5, adders 21, 22, subtracter 2, sample and hold circuits 31 and 32.

..., a block consisting of 8P cascade connection, adder 9,
A closed loop circuit consisting of the polarity detection circuit 10, the selector 11, and the switch 13 realizes the adaptive operation of the adaptive filter 25, and the pattern check circuit 12
controls the closed loop circuit to selectively update coefficients. The selector 11 is a pattern check circuit 1.
Based on the signal from the polarity detection circuit 2, either the output of the polarity detection circuit 10 or zero is selected and supplied to the switch 13. The switch 13 selects the output of the selector 11, the output of the selector 14, or the output of the switch 16 based on the sampling phase, and supplies the selected output to the adaptive filter 25. Next, the relationship between the output of the adder 9 and the residual intersymbol interference component in the difference signal that is the output of the subtracter 2 will be explained in detail.

FIG. 3 shows an example of a received signal eye pattern when the transmission line code shown in FIG. 2 is adopted. As shown in the figure, the received signal eye pattern has a rounded shape with high frequency components removed. Originally, the received signal eye pattern contains intersymbol interference components, but the eye pattern shown at the beginning to simplify the explanation is the one when waveform equalization is ideally performed. It shall not include any interfering components.

According to the characteristics of the received signal eye pattern shown in FIG. Waveform and M symbols (M is a positive integer)
This is when the data of the previous received signal waveforms match and the modes are different, and the received signals are canceled with a probability of 1/'4. Now, considering a non-ideal case, the received signal includes residual intersymbol interference components. Since the current residual intersymbol interference component and the residual intersymbol interference component before M symbols are uncorrelated, the residual intersymbol interference component before M symbols can be regarded as random noise. (2) The amplitude distribution of the residual intersymbol interference component before the symbol is symmetrical in sign and negative, and the probability that the amplitude d will be ldl < ε (however, 0 x ε) is not zero but takes a certain positive value. Therefore, it can be seen that the probability that only the residual intersymbol interference component is extracted as the output signal of the adder 9 takes a certain positive value that is not zero. Additionally, the magnitude of the residual intersymbol interference component is generally sufficiently small relative to the received signal. Therefore, the waveform shown in FIG. 3 can be regarded as the received signal waveform, even if it is not ideal.
5, and if the received signal that interferes with the adaptive operation of the adaptive filter 25 is canceled out, the adaptive filter 25
Adaptive operation of filter 25 will be guaranteed. Note that if the conditions that the current received signal waveform and the data of the received signal before M symbols match and the modes are different are not satisfied, the received signals will not cancel out. It is necessary to check the signal data and mode and stop the coefficient update. This coefficient update control is performed by the pattern check circuit 1.
2 and selector 11.

The pattern check circuit 12 detects that the data of the current received signal waveform and the received signal of the MT sand surface are equal and have different modes, and otherwise stops updating the coefficients of the adaptive filter 25. This can be realized by the circuit shown in FIG. A data signal 51 and a mode signal 52 constituting the output signal of the determiner 3 are input to this circuit. The mode signal 52 is the mode "+++, ti"
Corresponding to ++, the values are °°1'" and "0pa.

In addition, in FIG. 1, the determination 213 and the pattern check
check circuit 12, judger 3 and adaptive filter 25
The path connecting the data signal 51 and the mode signal 52 is shown as a single line, but if the MSK code is used, the data signal 51 and the mode signal 52
It has two routes corresponding to . A delay element 53 providing a delay of MT seconds and an exclusive exclusive OR circuit (XNOR) 55
It is checked whether the current signal and the data signal of the MT second sand surface signal match. This is the data signal 5
1 and a signal obtained by delaying the signal by MT seconds by the delay element 53, by performing a negative exclusive OR operation using the XN0R55. The output of XN0R55 is an AND circuit (AND>5
This is one input of 9. Similarly, the exclusive OR of the mode signal 52 and a signal delayed by MT seconds by the delay element 56 is taken by an exclusive OR circuit (X0R) 58, and the output is used as the other input of the AND5. AND 59 performs a logical product of the matching output of the data signal and the mismatching output of the mode signal to obtain a control signal 60 . The control signal 60 is supplied to the first selector 11. Note that the delay elements 53 and 56 providing a delay of MT seconds are realized by connecting M flip-flops in series.

The selector 11 receives a control signal 60 from the pattern check circuit 12, selects the output of the adder 9 or zero according to the control signal 6o, and supplies the selected output to the switch 13 and the selector 14. The selector 11 sends the output signal of the adder 9 to the switch 13
As described above, the pattern check circuit 12 supplies data to the selector 14 to check that the data of the current received signal and the MT seconds surface received signal match and that the modes are different.
is detected. When only the residual intersymbol interference component is accurately extracted by the selector 11 and the pattern check circuit 12, the residual intersymbol interference component is obtained as the output of the selector 11, and in that case, zero is obtained as the output of the selector 11.

On the other hand, the difference signal which is the output of the subtracter 2 is sent to the polarity determination circuit 15.
After the polarity of the difference signal is detected, it becomes an input to the switch 16. The switch 16 has four output contacts, and every T/R seconds (assuming R is an even number and R=4), the first output contact is switched from the first output contact to the fourth output contact.
Switch in the direction of the arrow in the figure and output. From the left in the figure, the first. Second. Third. The fourth output contact is used, and this operation is repeated every T seconds. The sampling phase of operation of switch 16 is shown in FIG. 3, at t. , 1.
．． 12 and 13 are respectively the first .
Second. Third. This corresponds to the sampling phase of the fourth output contact. The third contact output of the switch 16 is supplied as one of the inputs of the selector 14. Also, selector 1
The output of the selector 11 is supplied as the other input of the selector 4. On the other hand, a data signal, which is the determination result of the determiner 3, is input as a control signal to the selector 14.
When the data signal is "1", the third contact output of the switch 16 is selected and output, and when the data signal is "O'°, the output of the selector 11 is selected and output. That is, the output shown in FIG. As is clear from the waveform, when the data signal is "1", there is a zero crossing point at the center of the symbol, so the output of the third output contact of switch 16 shown in FIG. 1 becomes a residual intersymbol interference component. On the other hand, when the data signal is 0'' at t2, there is no zero crossing point at the center of the symbol, so it becomes a residual intersymbol interference component of the selector 11. Therefore, the output of the selector 14 is the third signal of the switch 13 as the residual intersymbol interference component of the sampling phase t2.
input contacts. The switch 13 is a switch having four input contacts, and in synchronization with the switch 16, switches from the first input contact to the fourth input contact every T/R seconds (assuming R=4 here). The input is sequentially switched in the direction of the arrow in FIG. 1 up to the input contact. From the left in the figure, the first. Second. Third. This operation is repeated every T seconds using the fourth input contact. 1 shown in Figure 3. ．． 1. ．． 12 and 13 are connected to the first .1 by switches 13 and 16 in FIG. Second
．． Third. This corresponds to the sampling phase of the fourth input contact. The first input contact of switch 13 is connected to switch 16.
The output of the selector 11 is supplied to the second and fourth input contacts, and the output of the selector 14 is supplied to the third input contact as described above. As shown in FIG. 3, sampling phase 1. Since no zero crossing point occurs at t3 and t3, the tap coefficients of the adaptive filter 25 are selectively updated using the residual intersymbol interference component obtained as the output of the selector 11 in FIG. Selecting zero in the selector 11 means that
This means that the tap coefficients are not updated, and corresponds to a case where no residual intersymbol interference component is obtained. Furthermore, at the sampling phase t2, the residual intersymbol interference components corresponding to the data signals '0' and '1' are obtained at the output of the selector 14 and supplied to the third input contact of the switch 13. Therefore, As the output of the switch 13, the residual intersymbol interference component necessary for updating the tap coefficient is obtained at each sampling phase and is supplied to the adaptive filter 25.In the above explanation, R=4, but R can be arbitrary. It is clear that the adaptive filter 25 may be an even number.Next, the adaptive filter 25 will be explained in detail.

FIG. 5 shows a block diagram of the adaptive filter 25 of FIG. The data signal 51, the mode signal 52, and the output signal 107 of the switch 13, which constitute the output signal of the determiner 3 in FIG. 1, are input to this filter. The mode signal 52 is transmitted through the delay element 1001 and the multiplier 10.
1o, 1011, -, 101R-1 and coefficient generator 10
2o.

102+, . . . , 102R-1. Also,
Data signal 51 is supplied to delay element 100'r and coefficient generators 102o, 102+, -, 102R-1. 100+ delay elements each providing a delay of T seconds
, 1002 ,..., 100 N/R-1 and 1
00'r, 100'2,..., 100'N
/R-1 are connected in this order, and each can be realized by a flip-flop. Here, the number of taps N is a positive integer, and R is a divisor of N. Further, the data period of the data signal 51 and mode signal 52 is T seconds. Delay element 100 l (i=1, 2..., N/R-
1> outputs are multipliers 101J and 101j+, respectively.
1. ..., 101 J+FL-1 and coefficient generator 102J, 102J, ..., 102 J+R-1
supplied to Moreover, the delay element 100 + (i=
1, 2. ..., N/R-1> are respectively supplied to the coefficient generators 102J, 102j+1 . ..., 102J
+R-1. However, j = i XR.

+ to multiplier 101 and 101; ,..., +N to 101
−R(k·0.l, . . . , R−1>), the coefficient generator 102 receives +a, .

After each coefficient which is the output of 102b+N-a is multiplied by the input mode signal (+1 or -1), all the multiplication results are input to the adder 103k and added. R adders 103o, 1031. −． The output of 103R-1 becomes a contact input of switch 104. The switch 104 is a multi-contact switch with a cycle of T seconds, and R adders 10
The outputs of 3o, 1031°, . do. On the other hand, a switch 105 that operates in synchronization with the switch 104 has an input/output direction opposite to that of the switch 104 . That is, the switch 105 switches the input signal 107 to T/
It performs the function of sequentially distributing to R contacts every R seconds. Each contact output of the switch 105 is supplied to a coefficient generator present in a signal path input to the contact corresponding to the switch 104 operating synchronously. Next, the coefficient generator will be explained in detail.

FIG. 6 shows the coefficient generator 102z (,/.0.l) of FIG.

..., N-1).

Mode signal 200 in FIG. 6 is similar to mode signal 52 in FIG.
or delay elements 100+, 1002,..., 10O
It corresponds to the mode signal output from N/R-1.

Similarly, the data signal 200' of FIG. 6 is the same as the data signal 51 of FIG. 5 or the delay element 100'! , 100′2 ,・
..., 100' Corresponds to the data signal output from N/R-1. Moreover, the error signal 201 in FIG.
This corresponds to the contact output of switch 105 in FIG. Furthermore, output signal 209 in FIG. 6 corresponds to the output of coefficient generator 1021 in FIG. In FIG. 6, a data signal 200' indicating "0" or "1" is supplied as a control signal to each of selectors 204, 205 and 208. In addition, " corresponding to the data signal 200'
A mode signal 200 taking +1'' or °゛-1'' is supplied as one of the inputs of a multiplier 202. On the other hand, the other input of the multiplier 202 is an error signal consisting only of residual intersymbol interference components. 201 is supplied. Multiplier 20
2, after the mode signal 200 and the error signal 201 are multiplied, the multiplication result is provided as one input of the adder 203.

Here, delay elements 206 and 207 giving a delay of T seconds
are coefficient memories corresponding to °"0°" and 1"' of the data signal 200', respectively, and their outputs are both sent to the selector 2.
08 input.

On the other hand, the data signal 200' is input to the selector 208 as a control signal, and the data signal 200' is "0".
When the data signal 200' is 1, the coefficient corresponding to the output of the delay element 206 is selected and output.
The coefficient corresponding to is selected and output, and in either case, an output signal 209 representing the coefficient is obtained. Furthermore, the output signal 20
9 is fed back to the adder 203, and after being added to the output signal of the multiplier 202, it is manually input to the selectors 204 and 205. Furthermore, the outputs of the delay elements 206 and 207 are
They are also supplied as inputs to selectors 204 and 205, respectively. Furthermore, the outputs of selectors 204 and 205 are
are supplied to delay elements 206 and 207, respectively. Next, the operations of selectors 204, 205 and 208 will be explained.

When the data signal 200' is "Opa", the selector 20
8 selects the output of the delay element 206 corresponding to the data signal "'0" and outputs it as an output signal 209. At this time, the output signal 209 is inputted to the adder 203 and then sent to the delay element 206 via the selector 204. The data is fed back to step 206, and the coefficient corresponding to the data "0" is updated. On the other hand, the selector 205 selects the output of the delay element 207 and supplies it again to the delay element 207, so the coefficient corresponding to data 1'' is not updated.Contrary to this case, , the data signal 200' is ".

1°', the selector 208 selects the output of the delay element 207, which is the coefficient corresponding to the data '1', and outputs it as the output signal 209. At this time, the output signal 20
After 9 is input to the adder 203, it is fed back to the delay element 207 via the selector 205, and the coefficient corresponding to data "1" is updated. On the other hand, the selector 20
4, the output of the delay element 206 is selected and supplied to the delay element 206 again, so the coefficient corresponding to the data "0°" is not updated. According to the principle explained above, the value of the data signal 200' is In addition to selecting the coefficients to be used in the adaptive filter operation corresponding to “0” or 1”, the coefficients that were used are updated, and the coefficients that were not used are returned to their original values. By holding , the coefficients of the adaptive filter can be obtained adaptively. Note that if only the residual intersymbol interference component is not extracted from the output of the adder 9 in FIG. 1, the coefficients of the adaptive filter 25 are not updated, and the error signal 2
01 becomes zero. At this time, as is clear from FIG. 6, since coefficient updating is stopped, convergence of the adaptive filter 25 is guaranteed. Adaptive filter 25
The pseudo intersymbol interference signal caused by the past data sequence generated in is supplied to the subtracter 2 via the adder 22, and is subtracted from the received signal that has received intersymbol interference and is supplied from the input terminal 1. . Next, interference cancellation within a symbol waveform will be explained.

Demodulated data, which is the output of the determiner 3, is input to the adaptive filter 18 via the polarity prediction circuit 23.
In FIG. 1, there is one line connected to the polarity prediction circuit 23, but in the case of the MSK code, there are two lines connected to the polarity prediction circuit 23 for supplying the data signal and mode signal. The polarity prediction circuit 23 is composed of one negative exclusive OR circuit, and calculates the negative exclusive OR of the data signal and the mode signal and supplies the result to the adaptive filter 18. Since the MSK code always inverts the polarity at the boundary of the waveform, the mode signal of the current received signal waveform can be known by using the mode signal that is the output of the determiner 3, which means the determination result of the received signal on the T sand surface. be able to. For example, the data signal is 0゛° and the mode signal is “1”.
When °゛ and the data signal is 1゛', the mode signal is “0”
In both cases, the polarity of the first half of the next symbol waveform is positive, and if this is defined as 0°', it matches the mode signal obtained as a negative exclusive OR. This is also clear from FIG. The output signal of the polarity prediction circuit 23 is used in the adaptive filter 18 as judgment data for the first half of the symbol waveform shown in FIG. On the other hand, the polarity of the difference signal that is the output of the subtracter 2 is input to the selector 17 via the polarity determination circuit 15 and the switch 16 at the sampling phase t2. Further, zero is also input to the selector 17, and using the judgment result that is the output of the judge 3, when the data signal is "ON", it is set to zero, and when it is "1", it appears at the third output terminal of the switch 16. The residual intersymbol interference component is selected and output, and is supplied to the adaptive filter 18. The selector 17 distinguishes that at the sampling phase t2, the symbol waveform representing data "O" does not have a zero crossing point, but always has data "1". The selector 17 supplies the polarity of the residual intersymbol interference component to the adaptive filter 18 when the data of the output signal of the determiner 3 is '1', and when the data is '0', the polarity of the residual intersymbol interference component is supplied to the adaptive filter 18. Coefficient updating occurs selectively only when ゛′. Of the displacement from zero at sampling phase t2, the component due to interference in the symbol waveform is added to the pseudo intersymbol interference signal generated by adaptive filter 18, which is added to adder 21.2.
2 to the subtracter 2, and is removed by subtracting it from the received signal subjected to intersymbol interference. Next, the adaptive filter 18 will be explained in detail.

FIG. 7 is a block diagram of the adaptive filter 18 shown in FIG. The input signal 300 in FIG. 7 is the output signal of the second output contact of the switch 16 in FIG. The polarity of the residual intersymbol interference component at the sampling phase t2 or the error signal that becomes zero corresponds to this. Further, the output signal 306 in FIG. 7 corresponds to the output signal of the adaptive filter 18 in FIG. 1, and is a pseudo intersymbol interference signal resulting from interference within the symbol waveform. In FIG. 7, the polarity of the difference signal 300 is provided to multipliers 302 and 305.

'The delay element 304 which provides a delay of seconds is a coefficient memory;
Its output is provided to a multiplier 305 to generate a pseudo intersymbol interference signal 306. The output of delay element 304 is also fed back through adder 303, and the polarity 30 of the difference signal is
The output of the multiplier 302, which multiplies the error signal by 0, is supplied to the adder 303. When the error signal 301 is zero, the output of the multiplier 302 is zero, so the coefficients do not change, and selective updating of the coefficients is performed. In this way,
The value of the pseudo intersymbol interference signal at the zero crossing at the center of the symbol waveform appears at the output of the adaptive filter 18, and is added to the pseudo intersymbol interference signal generated by the adaptive filter 5 in the adder 21. Vessel 22
is supplied to the subtracter 2 via the subtracter 2.

The adaptive filter 20 has the role of removing intersymbol interference that occurs at zero crossing points at the ends of the same symbol waveform due to the waveform within the symbol. The determiner 19 receives the difference signal that is the output of the subtracter 2, and determines the sampling phase t for the waveform within 3T/4 seconds in the first half of the symbol waveform with a period of T seconds.
3, the data and mode are determined, and the obtained temporary demodulated data is supplied to the adaptive filter 20. Further, the first contact output of the switch 16 is supplied to the adaptive filter 20 via the polarity determination circuit 15. Therefore, the sampling phase t. , the polarity of the difference signal output from the subtracter 2 is input to the adaptive filter 20 and used as an error signal for updating coefficients. As shown in FIG. 3, in an ideal case without intersymbol interference, the sampling phase t is the end of the symbol waveform. is a zero crossing point, but in reality, the amplitude at 1o does not become zero because intersymbol interference occurs. This difference is the intersymbol interference component, and the signal supplied from the output contact of the switch 16 matches the polarity of the intersymbol interference component.

FIG. 8 is a block diagram of adaptive filter 20 of FIG. 1. The basic configuration corresponds to one tap and one phase of the adaptive filter 25 in FIG. Therefore, the operating principle of coefficient updating is exactly the same as that shown in FIG.

In FIG. 8, functional blocks or signals indicated by the same reference numerals as in FIG. 6 are also the same. However, data signal 2
12' and mode signal 212 in the case of FIG.
This corresponds to the output of the determiner 19 in the figure. Furthermore, the error signal 213 in FIG. 8 corresponds to the output signal of the first output contact of the switch 16 in FIG. The difference between FIG. 8 and FIG. 6 is that the mode signal 212 and the output signal 20 of the selector 208
9 is performed in the multiplier 210, and a pseudo intersymbol interference signal 211 is output. Further, the error signal 201 in FIG. 6 takes three values, +1 and O, but in FIG. 8, it takes two values, +1. The pseudo intersymbol interference signal, which is the output of the adaptive filter 20 constituted by the circuit shown in FIG.

In Figure 1, sample and hold circuits 8+ and 8z are shown.

..., only the residual intersymbol interference component is extracted by the block consisting of 8p cascade connection and the subtracter 9, but the third
As is clear from the eye pattern in the figure, the adder 9 is replaced with a subtracter, and a negative exclusive OR circuit is used in place of the XOR 58 for detecting the mismatch of mode signals in the circuit shown in FIG. A similar effect can be obtained by detecting coincidence of signals. Also, in FIG. 1, sample and hold circuits 81, 82 . ..., it was assumed that the time required for sampling 8p was negligible, but if this assumption did not hold, the number of sample-and-hold circuits would be 1 [1
It is sufficient to prepare 1T/(T-861 month) or more.

Here, δ is the time required for sampling by the sample-and-hold circuit, [X] is the largest integer not exceeding X, and p = MXR
It is. The sampling period of each sample-and-hold circuit is always equal to T/R. Now, the phases of adjacent sample-and-hold circuits are shifted from each other by (T/R-δ).

At this time, one sample-and-hold circuit holds the sample value for (T/R-δ) seconds, which is the time δ required for sampling. For example, M=1. R・4. δ
・At T/32, the number of sample and hold circuits is 5.
If 5 sample/hold circuits are connected in series, the total hold time is 35T/3.
It becomes 2. This is the maximum hold time that can be achieved by connecting five sample and hold circuits in series.

In order to make the entire hold time T, the sample phases of adjacent sample-and-hold circuits may be sequentially shifted by T15. In addition, the sample phases of the four sample and hold circuits are sequentially shifted by 7T/32, and the remaining one is shifted by 4T/32 with respect to the sample phase of the previous sample and hold circuit.
Even if it is shifted, the overall hold time can be set to T. In this way, by appropriately shifting the sample phases of adjacent sample-and-hold circuits, the overall hold time can be reduced to T. Similarly, any hold time can be obtained for any δ smaller than T/R by connecting a sufficient number of sample-and-hold circuits in series and selecting the sample phase appropriately. Therefore, even if the time generally required for sampling cannot be ignored, any hold time that is an integral multiple of T can be obtained.

Although the present invention has been described above in detail using the MSK code as an example, a biphase code, for example, can be used as the transmission line code. When a bi-phase code is used, the received signal is a waveform obtained by shifting the received signal waveform shown in Figure 3 by T/2 seconds, so the pattern check method must be unique to the bi-phase code. . If the pattern check circuit 12 is configured as a logic circuit that outputs "1" only when it detects a combination of waveforms that cancel out the received signals, it can be used as a pattern check circuit for the MSK code shown in FIG. Can be used equally. However, in the case of a biphase code, the input signal to the pattern check circuit is only a data signal. In the case of a biphase code, selector 1
4 control signals are different from the MSK code. That is, the third
The selector 14 selects the output signal depending on whether the received signal takes a value of zero or not at the sample point t2 in the figure, but in the case of a bi-phase code, t2 is the boundary of the symbol waveform, so two consecutive It is necessary to use a circuit for controlling the selector 14 in accordance with the symbol waveform. Considering transmission line codes other than these codes in the same way,
It is clear that by detecting a pattern in which received signals are canceled and controlling updating of the coefficients of the adaptive filter 25, it is possible to accurately extract the residual intersymbol interference component with a certain probability.

〔Effect of the invention〕

As described in detail above, according to the present invention, by calculating the sum or difference between the current value and the MT second value for the difference signal, the residual intersymbol interference component included in the received signal is reduced to non-zero. Extracted accurately with probability of positive value. Therefore, by using the above sum or difference and further detecting a continuous pattern of the received signal waveform such that the residual intersymbol interference component can be extracted accurately, the sum or difference and the difference signal are calculated in accordance with the sampling phase. Adaptive operation is guaranteed by controlling an adaptive filter by updating coefficients while selecting, and provides a method and apparatus for removing intersymbol interference using decision feedback that is simple and does not require complicated control and has small hardware scale. can. Further, according to the present invention, it is possible to match the zero crossing points of the received signal with the sample points and simultaneously eliminate not only intersymbol interference caused by past symbol waveform sequences but also interference within symbol waveforms. It has the advantage that the judgment timing phase can always be optimally maintained regardless of the transmission distance and is resistant to clock jitter.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the symbol waveform and state transition of an MSK code, FIG. 3 is a diagram showing an eye pattern corresponding to the MSK code, and FIG. 4 is a diagram showing an eye pattern corresponding to the MSK code.
5 is a block diagram showing the pattern check circuit in FIG. 1, FIG. 5 is a block diagram of the adaptive filter 25 in FIG. 1, FIG. 6 is a block diagram of the coefficient generator in FIG. 7 is a block diagram of the adaptive filter 18 in FIG. 1, FIG. 8 is a block diagram of the adaptive filter 20 in FIG. 1, and FIG. 9 is a block diagram showing a conventional example of a decision feedback type equalizer. It is a diagram. 1... Input terminal, 2... Subtractor, 3.19... Determiner, 4... Output terminal, 5, 18.20.25...
Adaptive filter, 81, 82. ..., 8p.
...Sample/hold circuit, 9,21.22...Adder, 10.15...Polarity detection circuit, 11,14.1
7...Selector, 12...Pattern check circuit, 13.16...Switch, 23...Polarity detection circuit. Figure 2 Figure 3 to Z+ τ2 τ3 Figure 4 Figure 6 Figure 7 OI

Claims (2)

[Claims] (1) After subtracting the pseudo intersymbol interference signal from the received signal that has undergone intersymbol interference to obtain a difference signal, add or subtract the difference signal and a delayed signal that delayed the difference signal to cause residual intersymbol interference. component, and a first adaptive filter selects either the polarity of the residual intersymbol interference component or the polarity of the difference signal based on the sampling phase and the demodulated data sequence obtained by demodulating the difference signal. When the polarity of the residual intersymbol interference component is selected, the coefficients are updated only when a specific pattern of the demodulated data sequence is detected, and the second adaptive - A filter receives the polarity of the difference signal and the polarity of the first half of the next symbol waveform predicted from the demodulated data series, updates the coefficients only when the demodulated data series reaches a specific value, and performs a third adaptive filter. Before the symbol waveform of the difference signal is completely received by the filter, the coefficients are updated in response to the polarity of the difference signal and the provisional demodulation data sequence obtained by demodulating the symbol waveform of the difference signal, and the coefficients are updated. An intersymbol interference removal method using decision feedback, characterized in that the pseudo intersymbol interference signal is generated by adding the outputs of the adaptive filters. (2) a subtracter for obtaining the difference between the received signal and the pseudo intersymbol interference signal, a first determiner that receives the output of the subtracter and produces demodulated data, and the a first adaptive filter receiving demodulated data and a first error signal; a plurality of cascaded sample and hold circuits for sampling and holding the output of the subtracter; and an output of the subtracter; an arithmetic unit for obtaining the sum or difference with the outputs of the cascaded sample-and-hold circuits; a first polarity detection circuit for detecting the polarity of the output signal of the arithmetic unit; and the first polarity detection circuit. a first selector that selects either the output of the subtracter or zero; a pattern check circuit that receives the demodulated data and generates a signal that switches the first selector; and a pattern check circuit that detects the polarity of the output signal of the subtracter. a second polarity detection circuit; a first switch that distributes the output of the second polarity detection circuit based on the phase of the received signal; and a first switch that receives the demodulated data and predicts the polarity of the first half of the next symbol waveform. a polarity prediction circuit; a second adaptive filter that receives a prediction signal and a second error signal supplied from the polarity prediction circuit; a second selector that selects based on the demodulated data; a third selector that selects either the output of the first selector or the one contact output of the first switch based on the demodulated data; a second switch that selects one of the output of one output contact of the switch, the output of the first selector, and the output of the third selector based on the phase of the received signal;
a second determiner that receives the output of the subtracter and generates temporary demodulated data before completely receiving the symbol waveform of the output of the subtracter; and an output of the second determiner and a third error signal. a third adaptive filter receiving said first;
an adder that adds the outputs of the second and third adaptive filters to generate the pseudo intersymbol interference signal,
The output of the second switch is fed back to the first adaptive filter as the first error signal, and
The output of the selector is used as the second error signal.
An intersymbol interference removal device using decision feedback, characterized in that the signal is fed back to the third adaptive filter, and one contact output of the first switch is fed back to the third adaptive filter as the third error signal.