JPS6281143A - Synchronizing signal generating circuit by flag detection - Google Patents

Abstract

PURPOSE:To generate a synchronizing signal independently of number of flags by adopting the constitution that a synchronizing signal is formed from a leading output detected by a flag detection circuit and a trailing output delayed by a delay circuit in all cases where number of flags is >=1. CONSTITUTION:Every time a flag is detected from a reception data, a detection circuit 1 outputs a pulse of 1-bit length. A delay circuit 2 retards an output pulse of the detection circuit 1 by bit number of a flag pattern. A both-extreme detection circuit 3 collates an output of the detection circuit 1 with an output of the delay circuit 2 logically, the 1st pulse outputted from the detection circuit 1 is used as a leading output and the trailing pulse outputted from the delay circuit 2 is used as a trailing output, they are fed to a synchronizing signal generating circuit 4. The synchronizing signal generation circuit 4 outputs a synchronizing signal while the leading output of the both-extreme detection circuit 3 is used as a start point and the trailing output is used as a stop point.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a synchronization signal generation circuit based on flag detection in a data communication receiving device.

More specifically, the present invention is such that the synchronization signal can always be output using one or more flags, regardless of the number of successive reception flags.

(bl Conventional technology and problems) A flag detection circuit that separates a specific pattern of flags from an input signal inputs the input signal bit by bit into the flag detection circuit, compares it with a preset flag pattern, and separates the flag. do.

However, in conventional technology, when there is a plurality of flags, it is necessary to count the number of flag detections in order to detect the boundary between data and flags. There is a problem in that a synchronizing signal can only be generated in one case, and a synchronizing signal cannot be generated in other cases.

(C) Object of the Invention The object of the present invention is to provide a synchronization signal generation circuit that can generate a synchronization signal regardless of the number of flags when receiving human data having flags before and after the data.

(d) Examples of the invention First, a configuration diagram of an embodiment according to the present invention is shown in FIG.

In FIG. 1, 1 is a detection circuit, 2 is a delay circuit, 3 is a both-end detection circuit, and 4 is a synchronization signal generation circuit.

Each time the detection circuit 1 detects a flag from the received data, the detection circuit 1 outputs 1
Outputs a bit-length pulse.

The delay circuit 2 delays the output pulse of the detection circuit 1 by the number of bits of the flag pattern.

The both-end detection circuit 3 logically compares the output of the detection circuit 1 and the output of the delay circuit 2, and sets the first pulse outputted by the detection circuit 1 as the leading edge output, and the final pulse outputted by the delay circuit 2 as the trailing edge output. It is added to the synchronization signal generation circuit 4 as an output.

The synchronizing signal generating circuit 4 outputs a synchronizing signal starting from the leading end output of the both ends detecting circuit 3 and stopping from the trailing end output.

Next, a time chart of the embodiment shown in FIG. 1 is shown in FIG.

(A) to (1j) in FIG. 2 are waveform diagrams of portions corresponding to the reference numerals assigned to each portion in FIG. 1, respectively.

FIG. 2(A) shows the waveform of received data, in the case where there are three flags and the number of flag nodes is 8 bits.

FIG. 2(a) shows the waveform of the output pulse of the detection circuit 1,
Pl is the tip output output from the detection circuit 1.

Figure 2 (A) is the output of the delay circuit 2, and Figure 2 (A) is the output of the delay circuit 2.
are each delayed by 8 pins, which is the number of flag bits.

P2 in FIG. 2 is the rear end output of the pulse delayed by the delay circuit 2.

Figure 2 (1) and Figure 2 (1) are the outputs of the both ends detection circuit 3, and the tip output P1 in Figure 2 (A) and Figure 2 (
This is a pulse corresponding to the rear end output P2 (1).

FIG. 2(h) shows the output waveform of the synchronization signal generation circuit 4,
The rising edge of the pulse shown in FIG. 2 (I) is the start signal, and the signal L is the rising edge of the pulse shown in FIG. 2 (E) as the stop signal.

Next, a circuit diagram of the embodiment shown in FIG. 1 is shown in FIG.

The detection circuit l shown in Fig. 3 is composed of an 8-bit shift register, an inverting amplifier, and an 8-manufactured AND gate.
The AND gate outputs a 1-bit long pulse when the received data is rolllllloJ.

The delay circuit 2 is composed of an 8-bit shift register, and the shift register delays the output of the AND gate of the detection circuit 1 by 8 bits.

The both-end detection circuit 3 is composed of two inverting amplifiers and two AND gates, and the two AND gates output the front end output P1 of the detection circuit 1 and the final rear end output P2 output from the delay circuit 2, respectively.

The synchronization signal generation circuit 4 is composed of a flip-flop, and the flip-flop is set or reset by the output of two AND gates of the both-end detection circuit 3 and outputs a synchronization signal.

Next, a time chart of the embodiment shown in FIG. 3 is shown in FIG.

FIG. 4(A) shows received data, and shows a waveform when the flag pattern is "rollllllo".

Figure 4 (a) - Figure 4 (force) are shown in Figure 2 (a) - Figure 2 (
force) has the same waveform.

(d) Effect of the Invention According to this invention, in all cases where the number of flags is one or more, a synchronization signal is generated from the leading end output P1 detected by the flag detection circuit and the trailing end output P2 delayed by the delay circuit. This makes it easy to detect flags, and the number of leading/leading flags that arrive earlier than the data is different from the number of trailing flags that arrive later than the data. A synchronization signal can be generated even if

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment according to the present invention, and FIG.
3 is a circuit diagram of the embodiment shown in FIG. 1, and FIG. 4 is a time chart of the embodiment shown in FIG. 3. 1...Detection circuit, 2...Delay circuit, 3
...Both ends detection circuit, 4...Synchronization signal generation circuit. Agent Patent Attorney Kin Tsukasa Komata #I 1 Figure 2 Figure C)

Claims (1)

[Scope of Claims] 1. A flag detection circuit that detects a flag from received data and outputs a 1-bit length pulse; and a delay circuit that delays the output of the flag detection circuit by the number of bits of the flag; a both-end detection circuit which receives the output of the flag detection circuit and the output of the delay circuit as input, has a first output of the flag detection circuit as a leading end output, and has a final output of the delay circuit based on the flag as a trailing end output; 1. A flag-based synchronization signal generation circuit, comprising: a signal generation circuit which takes the output of the detection circuit as an input, uses the leading end output as a start, and uses the trailing end output as a stop to generate a synchronizing signal.