KR970064047A - Tandem Connection Data Link Processing Unit - Google Patents

Tandem Connection Data Link Processing Unit Download PDF

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Publication number
KR970064047A
KR970064047A KR1019960003524A KR19960003524A KR970064047A KR 970064047 A KR970064047 A KR 970064047A KR 1019960003524 A KR1019960003524 A KR 1019960003524A KR 19960003524 A KR19960003524 A KR 19960003524A KR 970064047 A KR970064047 A KR 970064047A
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KR
South Korea
Prior art keywords
data
unit
data link
frame
lomf
Prior art date
Application number
KR1019960003524A
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Korean (ko)
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KR100214052B1 (en
Inventor
채희문
Original Assignee
정장호
Lg 정보통신 주식회사
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Priority to KR1019960003524A priority Critical patent/KR100214052B1/en
Publication of KR970064047A publication Critical patent/KR970064047A/en
Application granted granted Critical
Publication of KR100214052B1 publication Critical patent/KR100214052B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)

Abstract

본 발명은 동기식 장치에서 직렬 접속을 시행할때 데이타 링크중 TC-APId #1~#16, 프레임 어리인먼트(Frame Alignment)신호인 TC-RDI, ODI비트를 검출하여 처리하기 위한 데이타 링크 처리장치에 관한 것이다. 종래의 동기식 장치에서 직렬 접속을 시행할때 데이타 링크를 처리하는 장치가 구비되어 있지 못하므로 TC-APId를 검출할 수가 없기 때문에 데이타의 연결이 원활하지 못한 문제점이 있었다. 이를 해결하기 위해 본 발명은 동기식 장치에서 직렬 접속을 시행할때 데이타 링크중 TC-APId #1~#16, 프레임 어라이먼트(Frame Alignment)신호인 TC-RDI, ODI 비트를 검출하기 위해 데이타 래치부, 프레임 검출부, 어드레스 생성부, LOMF 선언부 및 TC 데이타 래치부가 구비된 간단한 회로 구성으로서 데이타 링크중 TC-APId를 용이하게 검출할 수 있도록 한 것이다.The present invention relates to a data link processing device for detecting and processing TC-APId # 1- # 16, frame alignment signal (TC-RDI, ODI bit) in a data link when a serial connection is performed in a synchronous device, . There is a problem that data connection is not smooth because TC-APId can not be detected because a device for processing a data link is not provided when a serial connection is performed in a conventional synchronous device. In order to solve the above problems, the present invention provides a data latch circuit for detecting TC-APId # 1 to # 16, TC-RDI, and ODI bits, which are frame alignment signal, , A frame detecting unit, an address generating unit, a LOMF declaration unit, and a TC data latch unit, so that the TC-APId in the data link can be easily detected.

Description

직렬 접속(Tandem Connection)데이타 링크 처리장치Tandem Connection Data Link Processing Unit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 위한 데이타 링크 처리장치의 브럭 구성도1 is a block diagram of a data link processing apparatus according to the present invention;

Claims (1)

N1 TIME데이타와 클럭(6M CLK)의 동기가 일치할 경우 N1 DATA를 래치하는 데이타 래치부(1)와, 상기 데이타 래치부(1)에서 래치된 데이타중 FF, FE를 찾아서 존재할 경우 프레임이 맞는 것으로 선언하고 데이타중에 FF, FE가 계속해서 존재하지 않을 경우 프레임이 없는 것으로 선언하는 프레임 검출부(2)와, 상기 프레임 검출부(2)에서 프레임이 맞은 것으로 선언하면 그때부터 어드레스를 생성하여 후단의 LOMF 선언부(4) 와 TC 데이타 래치부(5)에 출력시키는 어드레스 생성부(3)와, 상기 어드레스 생성부(3)으로부터 0번 어드레스가 들어올때마다 상기 프레임 검출부(2)에서 도래하는 신호를 체크하여 프레임이 존재하지 않는다는 신호를 3 번 받을 경우 LOMF를 선언하는 LOMF선언부(4)와, 상기 데이타 래치부(1)에서 출력되는 데이타 상태에 따라 상기 어드레스 생성부(3)에서 출력되는 어드레스 중 어드레스 1~16은 TC-APId#1~#16을 래치하고 어드레스17은 TC-RDI와 ODI를 래치하는 TC데이타 래치부(5)로 구성된 것을 특징으로 하는 직렬 접속(Tandem Connection)데이타 링크 처리장치.A data latch unit 1 for latching N1 DATA when the synchronization of the N1 TIME data and the clock 6M CLK coincide with each other, and FFs and FEs of the data latched by the data latch unit 1, A frame detection unit 2 for declaring that the frame is not present if FF and FE do not exist continuously in the data, and a frame detecting unit 2 for generating an address from the frame detection unit 2, An address generation unit 3 for outputting the signal to be output from the frame detection unit 2 every time the address 0 is input from the address generation unit 3 to the declaration unit 4 and the TC data latch unit 5, A LOMF declaration section 4 for declaring a LOMF when a signal indicating that a frame does not exist is received three times and a LOMF declaration section 4 for issuing a LOMF declaration to the address generation section 3 according to the data state output from the data latch section 1 And a TC data latch unit 5 for latching TC-RDI and ODI at an address 17, wherein addresses 1 to 16 of the output addresses latch TC-APId # 1 to # 16, Data link processing unit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960003524A 1996-02-14 1996-02-14 Tandem connection data link processor device KR100214052B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960003524A KR100214052B1 (en) 1996-02-14 1996-02-14 Tandem connection data link processor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960003524A KR100214052B1 (en) 1996-02-14 1996-02-14 Tandem connection data link processor device

Publications (2)

Publication Number Publication Date
KR970064047A true KR970064047A (en) 1997-09-12
KR100214052B1 KR100214052B1 (en) 1999-08-02

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Application Number Title Priority Date Filing Date
KR1019960003524A KR100214052B1 (en) 1996-02-14 1996-02-14 Tandem connection data link processor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333581B1 (en) * 1998-01-07 2002-04-24 포만 제프리 엘 Tandem operation of input/output data compression modules

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333581B1 (en) * 1998-01-07 2002-04-24 포만 제프리 엘 Tandem operation of input/output data compression modules

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Publication number Publication date
KR100214052B1 (en) 1999-08-02

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