KR970029764A - FIFO memory read control circuit - Google Patents

Abstract

The present invention determines whether the data read from the FIFO memory is synchronous data because the operating frequency is high, and if the synchronous data is detected, even if the operation of supplying the read enable signal to the FIFO memory is not performed within one clock, the synchronous signal is enabled. The present invention relates to a read control circuit of a FIFO memory capable of waiting for the output of the FIFO memory until the present invention.

According to the present invention, a read control circuit includes a plurality of latches for sequentially latching and outputting an output of a FIFO memory, a plurality of synchronization data detectors for detecting synchronization data by receiving respective data latched by the plurality of latches, and a FIFO memory. Logic combination unit for generating a read enable signal that can wait for the output of the FIFO memory when the synchronization signal is enabled in the non-empty state or when synchronization data is not detected through the plurality of synchronization data detection units; The latch is configured to latch and output the enable signal by one clock. Therefore, the present invention can match the data processing period read from the FIFO memory even when the operating frequency is high.

Description

FIFO memory read control circuit

As this is a public information case, the full text was not included.

5 is a block diagram showing a read control circuit of a FIFO memory according to a preferred embodiment of the present invention.

Claims (4)

A read control circuit of a FIFO memory for use in a system having a high operating frequency, the read control circuit comprising: a plurality of latches for sequentially latching and outputting data read from the FIFO memory; A plurality of sync data detectors for receiving the data latched from the plurality of latches to detect sync data; Under the condition that the FIFO memory is not empty, the data read operation of the FIFO memory is performed when a valid synchronization signal is applied from the system for data processing or when no synchronization data is detected by the plurality of synchronization data detection units. A storage data empty state signal of the FIFO memory, a synchronization signal from a data processing system, and a plurality of the plurality of synchronization data detection units in order to make the data read operation of the FIFO memory stand by when at least one of the plurality of synchronization data detection units is detected. A logical combination unit for logically combining the synchronous data detection signals of the synchronous data detection unit; And a latch for latching a logic combination signal of the logic combination section and outputting the signal as a read enable signal of a next clock. The method of claim 1, wherein the plurality of latches receive and output a read enable signal output from the latch as an enable terminal to latch and output the input data for each block every data read operation of the FIFO memory. A read control circuit of a FIFO memory. 3. The apparatus of claim 2, wherein the plurality of sync data detectors comprises: a first sync data detector for detecting sync data from data latched by one clock of data latched in the plurality of latches; And a second synchronous data detector for detecting synchronous data from data latched by two clocks of the latched data. 4. The apparatus of claim 3, wherein the logic combination unit comprises: a first logical sum element for inverting the synchronous data detection signal of the second synchronous data detection unit and performing logical sum operation on the read enable signal output from the third latch; A first logical element for inverting the synchronous data detection signal of the first synchronous data detection unit and performing an AND operation on the logical sum operation signal of the logical sum element; A second logical sum element for performing logical sum operation on the synchronization signal supplied from the system by data processing and the logical product operation signal of the logical product element; And a second logical element which inverts a storage data bin state signal indicating whether the FIFO memory is empty and logically performs an AND operation on the logical sum operation signal of the second logical sum element, wherein the first synchronous data detection unit has a high operating frequency. Even after the synchronization data is detected, the second synchronization data detector detects the synchronization data and waits for data read operation of the FIFO memory until a valid synchronization signal is input after the synchronization data is detected. A read control circuit of a FIFO memory, characterized by outputting a read enable signal. ※ Note: The disclosure is based on the initial application.