KR100203260B1 - Fifo memory reading control circuit - Google Patents

Abstract

The present invention determines whether the data output from the FIFO memory is synchronous data due to the high operating frequency, and if the synchronous data is detected even if the operation of supplying the read enable signal to the FIFO memory is not performed within one clock, the synchronization signal is enabled. It relates to a read control circuit of the FIFO memory that can wait for the output of the FIFO memory until Therefore, the present invention can match the data processing period output from the FIFO memory even if the operating frequency is high.

Description

FIFO memory read control circuit

1 is a block diagram showing a FIFO memory and a FIFO memory read control circuit.

2 is a block diagram showing a general FIFO memory read control circuit.

3 is an operation timing diagram when the operating frequency of the circuit of FIG. 2 is low.

4 is an operating timing diagram when the operating frequency of the circuit of FIG. 2 is high.

5 is a block diagram showing a read control circuit of a FIFO memory according to a preferred embodiment of the present invention.

6 is an operation timing diagram of the circuit of FIG.

* Explanation of symbols for main parts of the drawings

51, 52, 56: Latch 53, 54: Synchronous data detection unit

55: logic combination OR1, OR2: logic element

AND1, AND2: logical product

The present invention relates to a read control circuit of a FIFO memory, and more particularly, to determine whether the read data from the FIFO memory is synchronous data due to a high operating frequency, and supplying a read enable signal to the FIFO memory according to the determination. The present invention relates to a read control circuit of a FIFO memory that causes a read operation from the FIFO memory to be in a waiting state until the synchronization signal is enabled, even if the synchronization data is not detected within one clock.

In general, FIFO memory is useful when the input / output time between two systems is not constant and variable. As shown in FIG. 1, in order to store data in the FIFO memory 10, a write enable signal (write enable) we is required. This write enable signal we is valid as long as the storage capacity of the FIFO memory 10 is not exceeded. That is, when the storage data full state signal ff is generated from the FIFO memory 10, the write enable signal we should not be valid so that data is no longer stored in the FIFO memory 10.

Here, if the stored data full state signal ff is at the high level represented by the binary signal 1, the stored data is full in the FIFO memory 10, and if the stored data is low level represented by the binary signal 0, it is still FIFO. The memory 10 is determined to be not full. Then, when the FIFO memory 10 is not full, the write enable signal we becomes a high level represented by the binary signal 1 so that the FIFO memory 10 stores the data A input thereto. On the other hand, in order to read the data stored in the FIFO memory 10, a read enable signal (read enable; re) is required. This read enable signal re is supplied from the read control circuit 20. The read control circuit 20 supplies the read enable signal re to the FIFO memory 10 when the stored data beam state signal (efty flag ef) is not generated from the FIFO memory 10 to supply the FIFO memory 10. Read saved data of. At this time, the FIFO memory 10 outputs data in the stored order. Then, if the data output from the FIFO memory 10 is the synchronous data, the read control circuit 20 stores the data of the FIFO memory 10 until the synchronization signal is supplied in the system for processing the data output from the FIFO memory 10. Control the read operation to the standby state. This is to match the data processing cycle output from the FIFO memory 10. The sync data is located at the head of the specific data, and the frame start code, the slice start code, the header, the macro block, and the sync of each sync block. (Sync) and so on. If the data output from the FIFO memory 10 is the synchronous data, the read control circuit 20 waits until the synchronous signal is input, and if the synchronous signal is input, the read control circuit 20 reads the data from the FIFO memory 10 until the next synchronous data is detected. Make it available for reading and processing. Therefore, the timing between the operation of outputting data stored in the FIFO memory 10 and the data processing operation can be matched. The read control circuit 20 is shown in more detail in FIG.

2 is a block diagram showing a read control circuit of a general FIFO memory. The read control circuit 20 includes a sync data detector 21 for receiving data output from the FIFO memory 10 and detecting sync data. The synchronous data detection unit 21 receives a valid synchronous signal from a system (not shown) that processes data output from the FIFO memory 10 while the FIFO memory 10 is not empty or outputs the FIFO memory 10. If the synchronous data is not detected from the FIFO memory 10, the stored data is read from the FIFO memory 10. If the synchronous data is detected, the read enable signal re for controlling the data read operation of the FIFO memory 10 to be in a standby state is read. A logic sum element (OR) 23 for inverting the synchronous data detection signal of the synchronous data detection unit 21 to perform a logical sum with the input synchronous signal for output, and the stored data beam state signal ef of the FIFO memory 10. It consists of a logical AND element (AND) 25 that is inverted and logically operated on the logical sum operation signal of the logical sum element 23.

In FIG. 2, the read control circuit 20 provides a high read effective enable level when the FIFO memory 10 is not empty, that is, when the storage data beam state signal ef is at a low level. Output the signal re. When a valid read enable signal re is applied from the read control circuit 20, the FIFO memory 10 sequentially outputs the stored data to the read control circuit 20 in the order of storage. On the other hand, when the FIFO memory 10 is empty, that is, when the storage data beam state signal ef is at the high level, the read control circuit 20 has an invalid read enable signal re of the low level. Outputs The FIFO memory 10 waits for a data read operation when an invalid read enable signal re is applied from the read control circuit 20.

The data B output from the FIFO memory 10 by the read control circuit 20 is input to the synchronous data detector 21 and supplied to a data processing system (not shown). The synchronous data detector 21 outputs a high level synchronous data detection signal represented by the binary signal 1 when the input data B is synchronous data, and a low level represented by the binary signal 0 when the data B is not synchronous data. Outputs the synchronous data detection signal of. The synchronous data detection signal is input to the inverting input terminal of the logic sum element 23. The logical sum element 23 inverts the synchronous data detection signal input to the inverting input terminal and logically operates the synchronous signal input from a data processing system (not shown). That is, the logic sum element 23 is a high level logic sum operation signal represented by binary signal 1 unconditionally when a valid synchronization signal of high level represented by binary signal 1 is input from a data processing system (not shown). Outputs On the other hand, when the invalid synchronizing signal is input, the logic sum element 23 outputs a high level logic sum operation signal represented by binary signal 1 when the synchronizing data detection unit 21 detects no synchronizing data, and synchronizes. When data is detected, a low level logic sum operation signal represented by binary signal 0 is output. As a result, after the synchronization data is detected, the data processing cycle can be synchronized by waiting for the data read operation of the FIFO memory 10 until a valid synchronization signal is input from the data processing system. The logical sum operation signal is input to the logical product element 25. The logical AND element 25 inverts the storage data beam state signal ef of the FIFO memory 10 by logical AND operation with the logical sum operation signal, and converts the logical AND operation signal into the read enable signal re. 10). That is, the logical multiplication element 25 is read-enabled to read data from the FIFO memory 10 in a state in which a valid synchronization signal is input or no synchronization data is detected, assuming that the FIFO memory 10 is empty. Output the signal.

In the read control circuit of the general FIFO memory operating as described above, the operation timing when the operating frequency is low is shown in FIG. In FIG. 3, (a) is a clock CLK, and (b) is a write enable signal we for write control of the FIFO memory 10. The FIFO memory 10 stores the input data A of FIG. 3 (C) in the high level section of the write enable signal we of FIG. 3 (B) and the clock CLK of FIG. Store in synchronization with rising edge of. Here, the write enable signal we of FIG. 3B is converted to a low level when the FIFO memory 10 is full so that the input data is no longer stored. The input data at this time is don't care and is indicated by hatching as shown in FIG. On the other hand, if the first data a is stored in the FIFO memory 10 in the state where the FIFO memory 10 is empty (the section in which the storage data beam state signal ef of FIG. 3 (D) is at a high level), The storage data beam bin state signal ef is at a low level. When the storage data beam state signal (ef in FIG. 3 (d)) is at the low level, the read control circuit 20 sets the read enable signal (reverse to FIG. 3 (d)) as high. It is applied to the FIFO memory 10 at the level. The FIFO memory 10 reads and reads the first data a stored in the FIFO memory 10 when the read enable signal re of FIG. 3 (e) applied from the read control circuit 20 is at a high level. Output to the control circuit 20. Here, the data B read from the FIFO memory 10 is as shown in FIG. The read control circuit 20 detects whether the data a read from the FIFO memory 10 through the sync data detector 21 is sync data. Here, when the data a is the synchronous data, the synchronous data has been detected by the synchronous data detector 21. Therefore, the inverse input of the logical sum element 23 and the logical operation by the logical product element 25 The read enable signal re is at a low level. As a result, the data read operation of the FIFO memory 10 becomes a standby state. In such a standby state, when a valid high-level synchronization signal (FIG. 3) is input from the data processing system (not shown), the logical operation by the logical sum element 23 and the logical product element 25 is performed. As a result, the read enable signal re in FIG. 3 (e) becomes a high level. Thus, data successive to synchronization data are output from the FIFO memory 10.

When the operating frequency is low as described above, if the synchronization data is detected from the data read from the FIFO memory 10 and an invalid read enable signal is applied to the FIFO memory 10 within one clock, the synchronization data is detected. The data read operation of the FIFO memory can be queued until the synchronization signal is enabled.

However, when the operating frequency is high, the read control circuit 20 detects the synchronous data a at the fourth clock of Fig. 4 from among the input data B of Fig. 4 (bar) read from the FIFO memory 10. As a result, the read enable signal re of FIG. 4 (e) is delayed by a predetermined state, and the state is converted to a low level and output. However, at the fifth clock of FIG. 4A, the read control circuit 20 determines that the synchronization data is not detected by the previously input data b. Thus, the read control circuit 20 converts the read enable signal re in FIG. 4 (e) to a high level. That is, since the operation frequency is high, it is detected whether the data output from the FIFO memory 10 is synchronous data, and the operation of outputting the read enable signal re to the FIFO memory 10 is not performed within one clock. . Thus, even if the synchronization data is detected, only the next data of the synchronization data is waited for one clock, and the data is continuously output from the FIFO memory 10. As a result, the synchronization of the data output from the FIFO memory 10 becomes inconsistent. In particular, when data is a video signal constituting a screen, the screen cannot be configured at all.

Accordingly, an object of the present invention is to detect whether the data output from the FIFO memory is synchronous data due to the high operating frequency, and if the synchronous data is detected even if the operation of outputting the read enable signal to the FIFO memory is not performed within one clock. The present invention provides a read control circuit of a FIFO memory capable of matching the data processing period by waiting for an operation of outputting data from the FIFO memory until a synchronization signal is applied from the outside.

The read control circuit of the FIFO memory according to the present invention for achieving the above object is a read enable signal for the data read operation for the FIFO memory used in the system having a high operating frequency, the storage data beam state signal and data of the FIFO memory A read control circuit of a FIFO memory generated using a synchronization signal from a processing system, comprising: a plurality of first latches for delaying and outputting data output from the FIFO memory by a predetermined clock based on a read enable signal; A plurality of sync data detectors for detecting sync data from each delayed data supplied from the plurality of first latches and outputting a sync data detection signal; Under the condition that the FIFO memory is not empty, a data read operation of the FIFO memory is performed when a valid synchronization signal is applied from a system for data processing or when synchronization data is not detected by all of the plurality of synchronization data detection units. And a stored data beam state signal of the FIFO memory, a synchronization signal from a data processing system, and the plurality of synchronization data detection units so that the data read operation of the FIFO memory becomes a standby state when at least one of the plurality of synchronization data detection units is detected. A logical combination unit for logically combining the synchronization data detection signals of the two synchronization data detection units; And a second latch for delaying a signal from the logic combiner for one clock and outputting the signal to the FIFO memory and the plurality of first latches.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram showing a read control circuit of the FIFO memory according to the present invention. As shown, the read control circuit of the present invention includes a latch 51 for delaying and outputting data B read from the same FIFO memory as shown in FIG. 1 by one clock, and a latch 51 delayed by one clock. A first synchronous data detector 53 for detecting whether each data is synchronous data in the data outputted from the data, a latch 52 for delaying and outputting the output data from the latch 51 by one clock, and a latch 52 And a second synchronous data detector 53 for detecting whether each data is synchronous data from the data outputted from the?

The read control circuit of the present invention also stores the stored data beam state signal ef of the FIFO memory, the synchronization signal from the data processing system (not shown), and the synchronization data detection signals of the plurality of synchronization data detection units 53 and 54. The logical combination signal 55 of the logical sum elements OR1 and OR2 and the logical AND elements AND1 and AND2 and the logical combination signal of the logical combination part 55 are read-read signals for the next clock. It is configured to include a latch 56 for outputting to the FIFO memory and the latches (51, 52) with a delay of one clock for use.

The operation of the read control circuit of the FIFO memory according to the present invention configured as described above will be described in more detail with reference to FIG.

FIG. 6 is an operation timing diagram of the circuit of FIG. 5, where FIG. 6 is a clock CLK, and FIG. 6 is a write enable signal we for write control of the FIFO memory. FIG. 6C is input data A for storing in the FIFO memory, and FIG. 6D is a storage data beam state signal ef for preventing underflow of the FIFO memory. FIG. 6E is a read enable signal re for reading stored data of the FIFO memory, FIG. 6B is data B output from the FIFO memory, and FIG. 51) is the data M output by delaying the input data B of FIG. 6 (bar) by one clock. FIG. 6 (A) shows data C which has delayed the input data M of FIG. 6 (G) by one clock through the latch 52 and outputs the data C. FIG. 6 (C) shows data C of FIG. Is a synchronization signal applied from a data processing system (not shown) that receives and processes.

First, the FIFO memory stores the data A of FIG. 6 (C) input from the outside in the section where the write enable signal we of FIG. Stored at each rising edge of clock CLK. That is, the write enable signal we of FIG. 6 (b) is performed when the initial FIFO memory is empty (the state in which the storage data beam state signal ef of FIG. When the high level is reached, the first data a of the data A of FIG. 6 (C) is stored on the FIFO memory in synchronization with the clock CLK 1 of FIG. Then, since the memory is not empty, the storage data beam state signal ef of FIG. 6D becomes a low level and is supplied to the read control circuit. If the stored data beam state signal ef of FIG. 6 (d) is at a low level, the read control circuit reads the data of the clock CLK 2 from FIG. The Able signal re is converted into a high level and output. The FIFO memory stores the stored data for each rising edge of the clock CLK of FIG. 6 in the period in which the read enable signal re of FIG. 6 (e) input from the read control circuit is at a high level. Read it. The data B of FIG. 6 (bar) read from the FIFO memory is input to the latch 51. The latch 51 receives the read enable signal re of FIG. 6 (e) supplied to the FIFO memory through the enable terminal ena to enable the latch operation only when data is read from the FIFO memory. The latch 51 reads each of the data B of FIG. 6 (bar) read from the FIFO memory in the period in which the read enable signal re of FIG. 6 (e) is a high level. Delayed by one clock for every clock CLK. Thus, the latch 51 reads the first data a of the data B of FIG. 6 (bar) from the FIFO memory in the clock CLK 3 of FIG. 6 (a), delays by one clock, and then closes the clock (CLK) 4. Outputs in synchronization with, and reads the second data b at the same time. The data M of FIG. 6 output from the latch 51 is input to the latch 52 and the first synchronous data detection unit 53. Here, the latch 52 is also supplied with the read enable signal re of FIG. 6 (e) supplied to the FIFO memory as the enable terminal ena, and the read enable signal re of FIG. 6 (e). The data M of FIG. 6 delayed by one clock through the latch 51 is delayed by one clock every clock CLK of FIG. . Thus, the latch 52 receives the first data a of the data M of FIG. 6 (G) output from the latch 51 at the clock CLK 4 of FIG. Outputs in synchronization with (CLK) 5, and at the same time, receives the second data b. At this time, the third data c of the data B of FIG. 6 (bar) read from the FIFO memory is input to the latch 51.

The data C of FIG. 6 (a) output from the latch 52 is input to the data processing system (not shown) and the second synchronous data detection unit 54. The first synchronous data detector 53 detects whether the current input data is the synchronous data among the data M of FIG. 6 (delayed by the latch 51), and the second synchronous data detector 54 is the latch 52. Detects whether the current input data is synchronous data among the delta C shown in FIG. The first synchronous data detector 53 outputs the clock of FIG. 6 (A) of the data M of FIG. 6 (G) output from the latch 51 in synchronization with the clock CLK 4 of FIG. When the first data a is detected in CLK) 5, it is determined as synchronous data and a high level synchronous data detection signal represented by binary signal 1 is output. At this time, since the synchronous data is not detected by the second synchronous data detection unit 54, the low level synchronization data detection signal represented by the binary signal 0 is output. The synchronous data detection signals x and y of the first synchronous data detection unit 53 and the second synchronous data detection unit 54 are input to the logical combination unit 55. Here, the logical combination unit 55 is configured to satisfy the logical expression of [! Ef (sync # (! X (! Y #re)))]. This is based on the condition that the FIFO memory is not empty and a valid high level 6th sync signal is input from the data processing system (not shown) or no sync data is detected. Has a logical configuration. More specifically, the logic combination unit 55 supplies the read enable signal re of FIG. 6 (e) and the synchronous data detection signal y of the second synchronous data detection unit 54 through the logic unit element OR1. Invert and logically combine (! Y # re). The AND product AND1 inverts the logical sum operation signal! Y #re of the logical sum element OR1 and the synchronization data detection signal x of the first synchronous data detection unit 53 to perform an AND operation (! X). (! y # re)). The logical OR element OR2 is a synchronous signal sync of FIG. 6 applied from a data processing system (not shown) and an AND operation signal (! X (! Y #re)) of the AND product AND1. Logical sum operation (sync # (! X (! Y # re))) AND logical element (AND2) is the logical sum operation signal (sync # (! X (! Y # re))) of the logical sum element (OR2) and FIFO The storage data beam state signal ef of FIG. 6D applied from a memory (not shown) is inverted and logically operated (! Ef (sync # (! X (! Y #re))).

Here, the logical AND device AND2 is a logical sum operation signal of the logical sum device OR2 when the FIFO memory is not empty (the storage data beam state signal ef of FIG. 6 (D) is in a low level state). In this way, the data read operation of the FIFO memory can be controlled. Then, the logical sum element OR2 is a FIFO memory when a valid synchronization signal (the sixth synchronization signal is high level) is applied from a data processing system (not shown) while the FIFO memory is not empty. If a valid synchronization signal is not applied, the data read operation of the FIFO memory can be controlled according to the AND operation signal of the AND product AND1. Here, the logical AND device AND1 and the OR1 have a first synchronous data detection unit 53 and a first FIFO memory regardless of whether the FIFO memory is empty and a valid synchronization signal is input from the data processing system in a read enable state. If the synchronization data is not detected from the data M of FIG. 6 (G) and the data C of FIG. 6 (A) by the synchronous data detection unit 54, the data read operation of the FIFO memory is performed, and the first synchronous data detection unit is performed. At least one of the 53 and the second synchronous data detector 54 controls the data read operation of the FIFO memory to be in a standby state even if the synchronous data is detected. When the synchronous data is detected by the first synchronous data detector 53, since the operating frequency is high, data other than the synchronous data is already input to the first synchronous data detector 53 at the next clock to detect the synchronous data. If not, it is determined. Therefore, since the same problem occurs as before, the synchronization data detection is performed once more through the second synchronization data detection unit 54.

That is, for example, in the four sections of the clock CLK of FIG. 6A, the logic sum element OR1 of the logic combination unit 55 is the read enable signal of FIG. 6E of the high level. A logical sum operation of the second synchronous data detection signal inverted to (re) and becomes a high level is output, and a logic level operation signal of a high level is output. The AND product AND1 performs an AND operation on the first synchronous data detection signal inverted from the high level first logical sum operation signal to become a low level, thereby performing a logical AND operation signal of a low level. Output The logic OR element OR2 performs a logical sum operation on an invalid sixth degree synchronization signal of a low level and a first logical operation signal of a low level, thereby performing a second logical sum operation of a low level. Output the signal. The AND product AND2 performs an AND operation on the storage data beam state signal ef of FIG. 6 (D), which is inverted from the low logic level second logical sum operation signal to become a high level, thereby causing a low ( Low) logical output operation signal is output. The latch 53 receives the second logical product signal of the low level of the logical AND device AND2 of the logical combination unit 55 and delays it by one clock, and the clock CLK of FIG. In synchronism with Fig. 5, the signal is output as a read enable signal re of FIG. 6 (e) in a low level state. When a low level read enable signal re is applied to the FIFO memory, the data read operation from the FIFO memory is stopped. The read enable signal re of FIG. 6E of the low level is also applied to the enable terminal ena of the latches 51 and 52 to stop the operation of the latches 51 and 52.

This is maintained for 6 sections of the clock CLK of FIG. 6A. Since the synchronization signal of FIG. 6C is high level at the rising edge of the clock CLK 7, the logic combination unit 55 The logic OR element OR2 unconditionally outputs a logic level operation signal of a high level.

The logic combination unit 55 inverts the logic sum operation signal of the high level to the high level and stores the storage data beam state signal ef of FIG. 6 (d) through the AND product AND2. The logical product operation outputs a logical combination signal of a high level. This is output via the latch 56 as the read enable signal re of FIG. 6 (e) of the high level to initiate the data read operation of the FIFO memory. As a result, in the clock CLK 8 of FIG. 6, the fourth data d of the data B of FIG. 6 is read from the FIFO memory, and the latch 51 outputs the third data c with delay. The latch 52 delays and outputs the second data b. After each clock, the next data is continuously read from the FIFO memory, and the latch 51 delays the data read from the FIFO memory by one clock, and the latch 52 delays the clock by one clock. Delay the output data by one clock again. However, in the clock CLK 14 of FIG. 6A, the latch 51 delays the synchronization data a by one clock, and thus outputs the latch 51 from the latch 56 at the clock CLK 15 to FIG. E) The read enable signal re becomes the low level so that the data read operation of the FIFO memory becomes a standby state. Then, the FIFO memory and the latches 51 and 52 are in a waiting state until a valid synchronization signal is inputted from the clock CLK 16.

As described above, the present invention relates to a read control circuit of a FIFO memory, and since the operation frequency is high and the operation of detecting the synchronization data and outputting the read enable signal is not performed within one clock, the synchronization signal is detected after the synchronization data is detected. In the conventional case where the data read operation of the FIFO memory was not waited until the input was completed, the read enable is enabled when the synchronous signal is input on the precondition that the FIFO memory is not empty. As a result, it is possible to detect synchronous data from the output data delayed by one clock and to read-disable using the read enable signal of the previous clock, thereby detecting the synchronous data and outputting the read enable signal within one clock. FIFO until sync signal is input after sync data is detected Can wait to read data from memory. Thus, data can be read from the FIFO memory at a data processing cycle.

Claims (4)

A read enable signal for a data read operation to a FIFO memory used in a system having a high operating frequency is applied to a read control circuit of a FIFO memory generated by using a storage data beam status signal of the FIFO memory and a synchronization signal from a data processing system. The plurality of first latches may include: a plurality of first latches configured to delay data output from the FIFO memory based on a read enable signal and delay the data output by a predetermined clock; A plurality of sync data detectors for detecting sync data from each delayed data supplied from the plurality of first latches and outputting a sync data detection signal; Under the condition that the FIFO memory is not empty, and if a valid synchronization signal is applied from a system for data processing or synchronization data is not detected by all of the plurality of synchronization data detection units, a data read operation of the FIFO memory is performed. And a stored data beam state signal of the FIFO memory, a synchronization signal from a data processing system, and the plurality of synchronization data detection units so that the data read operation of the FIFO memory becomes a standby state when at least one of the plurality of synchronization data detection units is detected. A logical combination unit for logically combining the synchronization data detection signals of the two synchronization data detection units; And a second latch for delaying a signal from the logic combiner for one clock and outputting the signal to the FIFO memory and a plurality of first latches. The display device of claim 1, wherein each of the plurality of first latches comprises: a third latch sequentially outputting data output from the FIFO memory by one clock; And a fourth latch for delaying and outputting the data output from the third latch by one clock, respectively. 3. The apparatus of claim 2, wherein the plurality of sync data detectors comprises: a first sync data detector for detecting sync data from data output from the third latch and outputting a sync data detection signal; And a second synchronous data detector for detecting synchronous data from the data output from the fourth latch and outputting a synchronous data detection signal. 4. The apparatus of claim 3, wherein the logic combination unit comprises: a first logical sum element for inverting the synchronous data detection signal of the second synchronous data detection unit and performing logical sum operation on the signal output from the second latch; A first logical element which inverts the synchronous data detection signal of the first synchronous data detection unit and performs an AND operation on the logical sum operation signal of the first logical sum element; a synchronization signal supplied from a system for data processing and the first logical product A second logical sum element for logical sum operation of the logical product operation signal of the element; And a second logical element for inverting a storage data beam state signal indicating whether the FIFO memory is empty, performing an AND operation on the logical sum operation signal of the second logical sum element, and outputting a logical product operation signal to the second latch. After the synchronization data is detected by the first synchronization data detector because the operating frequency is high, the synchronization data is detected by the second synchronization data detector, even though the synchronization data is not detected on the next clock. A read control circuit for a FIFO memory, characterized by outputting a read disable signal that waits for a data read operation of the FIFO memory until input.