JP3316882B2 - Pattern match / mismatch detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern match / mismatch detection circuit for high-speed transmission in a data communication line.

[0002]

2. Description of the Related Art Next, the configuration of a conventional pattern matching detection circuit will be described with reference to FIG. In FIG. 3, 1 is a shift register, 2 is a comparator, and 3 is a flip-flop (hereinafter referred to as F
Called F. ). The shift register 1 shifts the serial reception data signal 11 by the reception clock signal 12,
Output in parallel. The comparator 2 compares the output of the shift register 1 with the expected value, and the FF 3 outputs the coincidence signal 13 of the comparator 2.
Shape the waveform.

The shift register 1 shown in FIG. 3 shifts a received data signal 11 by a received clock signal 12, and generates parallel signals 21 to 24. The comparator 2 is a parallel signal 21
〜24 as a first input, and expected values 31-34 as a second input, corresponding signals are compared, and a match signal 13 is output when all signals match. FF3
Receives the coincidence signal 13 as a data input and outputs the coincidence signal 14 at the timing of the reception clock signal 12.

Next, the operation of FIG. 3 will be described with reference to the timing chart of FIG. FIG. 4A is a waveform diagram of the received data signal 11, and a serial signal is input to the shift register 1. FIG. 4A is a waveform diagram of the reception clock signal 12, and the data signal of FIG. 4A is shifted at the rise of the signal. In FIG. 3, since the shift register 1 has four stages,
The shift register 1 outputs the received data signal 11 sequentially shifted at the rise of the clock 12 in FIG. 4A as four data signals in parallel.

FIGS. 4A to 4C show the reception data signal 1 shown in FIG.
4 is a waveform of the received data signal 11 which is shifted in parallel by the shift register 1 and output in parallel. FIGS. 4A to 4C are shifted at every rising edge of the clock 12 in FIG. 4A to 4C show expected value data input in parallel to the comparator 2;
It is set in advance. 4 is set to “1”, FIG. 4 is set to “0”, FIG. 4 is set to “0”, and FIG. 4 is set to “1”.

FIG. 4 shows the waveform of the output of the comparator 2. The expected value of FIG. 4 is a bit string of "1, 0, 0, 1" and the received data 11 of FIG. And a match signal 13 is generated when they match. In FIG. 4, since the bit strings “1, 0, 0, 1” match at two locations, the match signal 13 is generated twice. FIG. 4 shows a waveform of the signal of FIG. 4 output at the falling timing of the signal of FIG.

[0007]

In the configuration shown in FIG. 3, the coincidence signal 13 is output when the input received data signal 11 matches the expected value, but the signal is not output in the non-coincidence state. According to the present invention, a period generating counter, a gate circuit, and a second FF are added to a pattern matching circuit including a shift register 1, a comparator 2, and a first FF 3.
When the coincidence signal 13 is not output from the comparator 2 and only the period signal is output from the period generation counter, the gate circuit outputs the non-coincidence signal. It is an object of the present invention to provide a pattern match / mismatch detection circuit for reliably detecting the state of the pattern.

[0008]

In order to achieve this object, according to the present invention, a shift register 1 which receives a received data signal 11 as a serial input and is shifted by a received clock signal 12 to output a parallel output, The output is the first input, the expected value is the second input, the first
And a second input comparing the first input with the expected value, and outputting a match signal 13 when the first input matches the expected value.
Of the comparator 2 as a load input, and a period generating counter 4 for generating a periodic signal 15 at the timing of the received clock signal 12.
A gate circuit 5 having the output of the period generation counter 4 as a first input and an inverted signal of the output of the comparator 2 as a second input; and a waveform of the output of the gate circuit 5 at the timing of the received clock signal 12. When the comparator 2 does not output the coincidence signal 13 and outputs only the periodic signal 15, the gate circuit 5 outputs a non-coincidence signal 16.

[0009]

Next, a pattern match / mismatch detection circuit according to the present invention will be described with reference to FIG. 1 is a cycle generation counter, 5 is a gate circuit, 6 is an FF, and the rest is the same as FIG. The gate circuit 5 is a counter 4 for generating a period.
The FF 6 shapes the waveform of the non-coincidence signal 16 from the gate circuit 5 by comparing the periodic signal 15 from the comparator 2 with the coincidence signal 13 from the comparator 2. That is, FIG. 1 is obtained by adding the period generation counter 4, the gate circuit 5, and the FF 6 to FIG.

The period generation counter 4 shown in FIG.
Is the load input, and the reception clock signal 12 is the timing input. The period generation counter 4 outputs a period signal 15 and serves as a first input of the gate circuit 5.

The period generating counter 4 generates a period signal 15 for each stage of the shift register 1. In FIG. 1, since the shift register 1 has four stages, the period generation counter 4 repeats "0" to "3". The coincidence signal 13 from the comparator 2 is inverted and becomes the second input of the gate circuit 5. The output of the gate circuit 5 is input to the FF 6 at the timing of the reception clock signal 12 as a mismatch signal 16,
The waveform is shaped and extracted as an output 17.

Next, the operation of FIG. 1 will be described with reference to the timing chart of FIG. 2A to 2C are the same as FIGS. 4A to 4C. FIG. 2 shows a cycle signal 15 output from the cycle generation counter 4. The coincidence signal 13 from the comparator 2 is used as the LD input of the period generation counter 4, and returns to the initial value by the coincidence signal 13. When the counter value becomes “3”, the period signal 15 is output. If the coincidence signal 13 is not output, the counter 4 repeats “0” to “3”, so that when the counter value becomes “3”, the periodic signal 15 is output. FIG. 2 shows an output signal of the gate circuit 5, wherein the period signal 15 of the period generation counter 4 and the coincidence signal 13 of the comparator 2 are shown.
The gate circuit 5 outputs a non-coincidence signal 16 when only the periodic signal 15 is output without outputting the coincidence signal 13 as an input.

[0013]

According to the present invention, a period generating counter, a gate circuit, and a second FF are added to a pattern matching circuit including a shift register, a comparator, and a first FF.
If the comparator does not output a coincidence signal but outputs only a periodic signal, the gate circuit outputs a non-coincidence signal. Therefore, it is possible to detect pattern non-coincidence or abnormality that cannot be detected by the pattern coincidence circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a pattern match / mismatch detection circuit according to the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a configuration diagram of a pattern matching detection circuit according to the related art.

FIG. 4 is a timing chart of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register 2 Comparator 3 FF (flip-flop) 4 Counter circuit 5 Gate circuit 6 FF (flip-flop)

Claims (1)

(57) [Claims] 1. A shift register (1) which receives a received data signal (11) as a serial input, shifts by a reception clock signal (12) and outputs a parallel output, and an output of the shift register (1) as a first input. A comparator (2) that compares an expected value with a second input, compares the first input with the second input, and outputs a match signal (13) when the first input matches the expected value; The output of (2) is input, the first flip-flop (3) for waveform shaping and the output of comparator (2) are load inputs, and the received clock signal
A period generation counter (4) that generates a period signal (15) at the timing of (12), and the output of the period generation counter (4) as a first input, and an inverted signal of the output of the comparator (2). Gate circuit as second input
(5) and a second flip-flop (6) for shaping the waveform of the output of the gate circuit (5) at the timing of the received clock signal (12), and the comparator (2) outputs the coincidence signal (13). The periodic signal (1
When only 5) is output, the gate circuit (5) outputs the mismatch signal (1
6. A pattern match / mismatch detection circuit which outputs 6).