CN102736888B - With the data retrieval circuit of synchronization of data streams - Google Patents
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- CN102736888B CN102736888B CN201210224661.3A CN201210224661A CN102736888B CN 102736888 B CN102736888 B CN 102736888B CN 201210224661 A CN201210224661 A CN 201210224661A CN 102736888 B CN102736888 B CN 102736888B
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Abstract
The invention discloses data retrieval circuit that is a kind of and synchronization of data streams, belong to field of information processing.Circuit: shift register is used under clock signal effect, each clock period receives a data cell in the data stream of input, and the data simultaneously deposited the previous clock period are a mobile data cell by turn; Sample register is used for pre-setting sample data, and sample data comprises some data cells; Mould 2 adds computing circuit and adds computing for the data in shift register and the data in sample register are carried out mould 2; Extract indicator register to be used to indicate mould 2 and to add significance bit part in the operation result of computing; Result is extracted and is added significance bit part in the operation result of computing with decision circuit for extracting mould 2; And whether retrieve the data consistent with sample data according to the judgement of significance bit part; If judgement for retrieving the data consistent with sample data, then produces matched signal.This circuit and synchronization of data streams are retrieved, and structure is simple.
Description
Technical field
The present invention relates to field of information processing, particularly a kind of data retrieval circuit with synchronization of data streams.
Background technology
Data retrieval is the common operation of information processing, relates to many application in the fields such as information retrieval, pattern-recognition, information security.The speed of data retrieval is directly connected to the performance of these application.
Existing data retrieval can be divided into software retrieval and hardware to retrieve two large classes.Software retrieval can only carry out on the basis that each cycle compares a character, and its deficiency is apparent.Compared with software retrieval, hardware retrieval can realize the parallel of multiple character and compare, and makes retrieving and synchronization of data streams become possibility.Wherein, the hardware retrieval technique based on automaton theory, due to its for be the serial processing of stream, so based on the data retrieval circuit not only complex structure of this technology, and degree of parallelism is not high, and retrieval rate is subject to significant restrictions.In order to improve retrieval rate, prior art provides a kind of character string retrieving circuit.Particularly, this character string retrieving circuit is based on pipelining, each cycle can carry out taking turns parallel comparison to n byte of input circuit and the sample being stored in dictionary in advance, but need the comparative result using previous round, and for the sample of m byte, each takes turns required intermediate result of preserving just m.
Realizing in process of the present invention, inventor finds that prior art at least exists following problem:
As everyone knows, the programmed logic of the serial processing of data stream that what pipelining was followed in essence remain, just performs the instruction rearward of position on streamline in advance thus reaches a kind of effect of parallel processing.In order to realize this " walking abreast " process, generally adopt forecasting techniques.For the streamline with the instruction of N road, the number of results that its each cycle is possible is 2
n, then the instruction of K road needs from 2
(K-1)correct prediction is selected in individual prediction.This greatly brings the complicacy of circuit.
Summary of the invention
Consider above-mentioned aspect, the present invention wants to release data retrieval circuit that is a kind of and synchronization of data streams, when data stream to be retrieved is out-of-date, only to compare with the parallel of sample data draw comparative result according to the current data of circuit that flow through, this comparison is with the transmitting synchronous of data, and does not need to rely on historical data completely.Based on this, the invention provides data retrieval circuit that is a kind of and synchronization of data streams, described technical scheme is as follows:
With a data retrieval circuit for synchronization of data streams, described circuit comprises:
Shift register, under clock signal effect, each clock period receives a data cell in input traffic, the data mobile simultaneously deposited previous clock period data cell;
Sample register, for pre-setting sample data, described sample data comprises some data cells; Described shift register is identical with described sample register length; And the length of described sample data is less than or equal to the length of described sample register;
Mould 2 adds computing circuit, adds computing for the data in the data in described shift register and described sample register are carried out mould 2;
Extract indicator register, be used to indicate described mould 2 and add significance bit part in the operation result of computing;
Result is extracted and decision circuit, adds significance bit part in the operation result of computing for extracting described mould 2; And whether retrieve the data consistent with described sample data according to described significance bit part judgement; If judgement for retrieving the data consistent with described sample data, then produces matched signal;
Wherein, described mould 2 add computing circuit specifically for,
Data cell corresponding in data cell in described shift register and described sample register is carried out mould 2 respectively and adds computing; I-th data cell corresponding in i-th data cell of data in described shift register and described sample register is carried out mould 2 to add computing and be,
M
i＝B
i⊕S
i＝(b
i0⊕s
i0)∨(b
i1⊕s
i1)∨……∨(b
i(N-1)⊕s
i(N-1))
Wherein, B
ifor i-th data cell of data in described shift register, S
ifor i-th data cell in described sample register, N is the width of described data cell, b
ijwith s
ijbe respectively described B
iwith described S
ia middle jth bit; M
ifor i-th data cell corresponding in i-th data cell of data in described shift register and described sample register being carried out the operation result that mould 2 adds computing, M
ibe specially boolean's data of a bit.
Wherein, the width size of described data cell is 1,8 or 16.
Wherein, described extraction indicator register specifically for,
Pre-set the designation data that the described mould 2 of instruction adds the live part of the operation result of computing; Described designation data is,
Wherein, the length of described sample data is m+1, and the length of described shift register is n+1, and m≤n; f
ifor i-th Bit data of described designation data.
Wherein, described result extract with decision circuit specifically for,
The data described mould 2 being added corresponding position in the operation result of computing and described designation data are carried out and computing respectively, extract described mould 2 and add significance bit part in the operation result of computing; Described mould 2 is added the i-th corresponding bit data in the operation result of computing and described designation data carry out with computing be,
C
i＝M
if
i
Carry out described or non-computational with each data in the operation result of computing, judge whether to retrieve the data consistent with described sample data according to operation result that is described or non-computational; Described or non-computational is,
Wherein, M
ifor i-th data cell corresponding in i-th data cell of data in described shift register and described sample register being carried out the operation result that mould 2 adds computing; C
ithe operation result with computing is carried out for described mould 2 being added the i-th corresponding bit data in the operation result of computing and described designation data; C
0, C
1..., C
m, C
m+1..., C
nbe respectively described with the operation result of computing in the 0th, 1 ..., m, m+1 ..., n-bit data; O is operation result that is described or non-computational;
As o=1, be judged as retrieving the data consistent with described sample data, produce matched signal;
As o=0, be judged as not retrieving the data consistent with described sample data, produce mismatch signal.
Wherein, described circuit also comprises counter and result cache circuit,
Described counter is used for, and counts the number of the data cell inputting described shift register,
Correspondingly, described result cache circuit is used for, when described result is extracted and decision circuit produces matched signal, and the current count value of counter described in buffer memory.
Wherein, described circuit also comprises serial-parallel conversion circuit,
Described serial-parallel conversion circuit is used for, when described input traffic be serial data stream and the width of described data cell be 8 or 16 time, described serial data stream is changed into the parallel data stream consistent with the width of described data cell; And described parallel data stream is sent into described shift register.
Wherein, described circuit also comprises clock trimming circuit,
Described clock trimming circuit is used for, and maintains described clock signal state constant during the current count value preserving described counter.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is: by relatively succinct circuit, sample retrieval length the data of design load can be no more than from data stream, and the input of data, retrieval and output are synchronously carried out, i.e. retrieval and digital independent or transmitting synchronous, cost is cheaper, cost-saving.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram of the data retrieval circuit of a kind of and synchronization of data streams provided in the embodiment of the present invention 1;
Fig. 2 is the schematic diagram of the data retrieval circuit of a kind of and synchronization of data streams provided in the embodiment of the present invention 2;
Fig. 3 is another schematic diagram of the data retrieval circuit of a kind of and synchronization of data streams provided in the embodiment of the present invention 2;
Fig. 4 is the schematic diagram of the displacement when input data are octet parallel data and the comparison procedure provided in the embodiment of the present invention 2;
Fig. 5 is the schematic diagram of the data retrieval circuit of a kind of and synchronization of data streams provided in the embodiment of the present invention 3;
Fig. 6 is the schematic diagram of the data retrieval circuit of a kind of and synchronization of data streams provided in the embodiment of the present invention 4;
Fig. 7 is the schematic diagram of the clock trimming circuit provided in the embodiment of the present invention 4.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
Embodiment 1
See Fig. 1, the embodiment of the present invention 1 provides data retrieval circuit that is a kind of and synchronization of data streams, and this circuit comprises: shift register 101, sample register 102, mould 2 add computing circuit 103, extraction indicator register 104 and result and extract and decision circuit 105.
Wherein, shift register 101 is under clock signal effect, and each clock period receives a data cell in the data stream of input, and the data simultaneously deposited the previous clock period are a mobile data cell by turn.
Wherein, sample register 102 is for pre-setting sample data; This sample data comprises some data cells.
Wherein, mould 2 adds computing circuit 103 and adds computing for the data in the data of shift register 101 and sample register 102 are carried out mould 2.
Wherein, extract indicator register 104, be used to indicate mould 2 and add significance bit part in the operation result of computing.
Wherein, result is extracted and is added live part in the operation result of computing with decision circuit 105 for extracting mould 2, and whether retrieves the data consistent with sample data according to the judgement of this significance bit part; If judgement for retrieving the data consistent with sample data, then produces matched signal.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is: by relatively succinct circuit, sample retrieval length the data of design load can be no more than from data stream, and the input of data, retrieval and output are synchronously carried out, i.e. retrieval and digital independent or transmitting synchronous, cost is cheaper, cost-saving.Due to simple circuit, its arithmetic speed also may faster than the circuit adopting prior art.
Embodiment 2
See Fig. 2 ~ Fig. 3, the embodiment of the present invention 2 provides data retrieval circuit that is a kind of and synchronization of data streams, this circuit comprises: shift register 201, sample register 202, mould 2 add computing circuit 203, extraction indicator register 204 and result and extract and decision circuit 205, and result cache circuit 206, counter 207.
Wherein, shift register 201 is under described clock signal effect, and each clock period receives a data cell in the data stream of input, and the data simultaneously deposited the previous clock period are a mobile data cell by turn.
Wherein, sample register 202 is for pre-setting sample data; This sample data comprises some data cells.
Wherein, mould 2 adds computing circuit 203 and adds computing for the data in the data of shift register 201 and sample register 202 are carried out mould 2.
Wherein, extract indicator register 204 to be used to indicate mould 2 and to add significance bit part in the operation result of computing.
Wherein, result is extracted and is added live part in the operation result of computing with decision circuit 205 for extracting mould 2, and whether retrieves the data consistent with sample data according to the judgement of this significance bit part; If judgement for retrieving the data consistent with sample data, then produces matched signal.
And, when needing to obtain the matched data that retrieves position in a stream, should also comprise result cache circuit 206 sum counter 207 with the data retrieval circuit of synchronization of data streams.
Wherein, counter 207, under described clock signal effect, counts the number of the data cell in input shift register 201.
Correspondingly, when result cache circuit 206 produces matched signal for extracting when result with decision circuit 205, preserve the current count value of counter 207 and set result cache be the notification signal of sky.Suppose this buffer memory not for empty notification signal is oe.
Particularly, the input termination data stream of shift register 201 and external clock.Shift register 201, under clock signal effect, deposits the data inputted in present clock period data stream; And a data cell of each clock period input traffic in clock signal, simultaneously by original data mobile data cell by turn, with upgrade in each clock period shift register data.
Particularly, the width size of the data cell described in the embodiment of the present invention 2 is 1,8 or 16.The width size of data cell is by the type decided needing retrieve data.Such as, the width of tentation data unit is N (N>0) bit; When data to be retrieved are binary data, N=1; When data to be retrieved be ASCII character character stream or 256 color pixel stream time, N=8; When data to be retrieved be 16 UNICODE character streams or 16 color pixel stream time, N=16.
Wherein, the data stream of this input is the data stream flowing through shift register 201 in transmission line; Or the data stream of this input is in data transmission or the data stream of the terminal inflow shift register 201 of input.What deserves to be explained is, if the data stream of this input is in data transmission or the data stream of the terminal inflow shift register 201 of input, then mean that namely data cell is dropped after shifting out shift register 201.
Further, shift register 201 is identical with sample register 202 length, and namely had deposit unit quantity is identical.Wherein, each deposit unit corresponding stored data cell.
Further, suppose that shift register 201 and sample register 202 length are n+1, if the length of sample data is m+1 (m≤n) individual data cell, if sample data from right to left i-th data cell be V
i.Particularly, suppose that sample data is V
mv
m-1v
1v
0, sample register 202 stores from the deposit unit on the most left side, as shown in Figure 3, is followed successively by V
0, V
1..., V
m.The remaining deposit unit in its right side is without the need to comprehending.Such as, when sample data is character string " ABCD ", then V is had
0=" D ", V
1=" C ", V
2=" B ", V
3=" A ", " D ", stored in the deposit unit on the most left side of sample register 202, turning right is followed successively by " C ", " B ", " A ", and remaining deposit unit is without the need to changing.
Wherein, mould 2 adds computing and carries out in units of data cell.Particularly, suppose that in shift register 201, i-th data cell is B
i, in sample register 202, i-th data cell is S
i, data unit width is N, b
ijwith s
ijbe respectively B
iwith S
ijth bit, with B
iwith S
imould 2 for operand adds operation definition,
M
i=B
i⊕ S
i=(b
i0⊕ s
i0) ∨ (b
i1⊕ s
i1) ∨ ... ∨ (b
i (N-1)⊕ s
i (N-1)) ... (1) wherein, M
ibe i-th corresponding data cell in i-th data cell in shift register 201 and sample register 202 and carry out the operation result that mould 2 adds computing.Can learn according to above-mentioned formula (1), no matter the width of data cell is much, and its two corresponding data cells carry out boolean's data that operation result that mould 2 adds computing is a bit, for representing two operand B
iwith S
iequal (M
i=0) or unequal (M
i=1).
Fig. 4, for 2 adjacent cells, describes displacement when being input as parallel octet data and compares concept.Wherein, i-th data unit B of shift register 201
iwhen the clock period, signal was effective, by each bit (b of its value
0, b
1, b
2, b
3, b
4, b
5, b
6, b
7) be assigned to the next data cell B of shift register 201
i+1each corresponding position, and accept a data cell B on shift register 201
i-+1transfer its value to.And work as B
iwith S
im time equal
ibe 0, otherwise be 1.
If shift register 201 is containing n+1 data cell, then mould 2 adds the operation result that computing circuit 203 has n+1 bit length.Obviously, when the length of sample data is less than n+1, this mould 2 adds in the operation result of computing and there is inactive portion.So, the significance bit part extracted in this operation result is needed.Wherein, this significance bit part finger print 2 adds all bits corresponding with each data cell of sample data in the operation result of computing.Further, extract the computing of effective result, its principle is as follows:
First, the designation data pre-setting instruction mould 2 and add the live part of the operation result of computing is extracted in indicator register 204.If i-th that extracts designation data in indicator register 204 is f
i.Corresponding to i-th data cell S in sample register 202
i; If sample data has the data of m+1 data unit length and is preset in 0 to the m deposit unit of sample register 202, i.e. S
0to S
m, then f
isetting specified by following formula:
Wherein, as 0≤i≤m, f
i=1, it is effective for representing that mould 2 adds data cell corresponding with each data cell of sample data in the operation result of computing.As m+1≤i≤n, f
i=0, other parts that the mould 2 representing except the data cell that each data cell with sample data is corresponding adds the operation result of computing are invalid.
Further, result extract with judgement computing circuit 205 specifically for, data mould 2 being added corresponding position in the operation result of computing and designation data are carried out and computing respectively, extract depanning 2 and add significance bit part in the operation result of computing; Undertaken with each data in the operation result of computing or non-computational, according to or the operation result of non-computational judge whether to retrieve the data consistent with sample data; If retrieve the data consistent with sample data, produce matched signal; If do not retrieve the data consistent with sample data, produce mismatch signal.
First, remember that with i-th of the operation result of computing be C
i(
i=0,1 ..., n).So, mould 2 is added the i-th corresponding bit data in the operation result of computing and designation data carry out with operation definition be,
C
i＝M
if
i＝(B
i⊕S
i)f
i
Obviously, work as i=m+1, m+2 ..., during n, C
ibe 0.
Secondly, if C
0, C
1..., C
m, C
m+1..., C
nbe respectively described with the operation result of computing in the 0th, 1 ..., m, m+1 ..., n-bit data; O is operation result that is described or non-computational; Then o is defined as,
Wherein, as o=1, be judged as retrieving the data consistent with described sample data, produce matched signal; As o=0, be judged as not retrieving the data consistent with described sample data, produce mismatch signal.
Visible, court verdict is only determined, and if only if all C by the front portion corresponding with sample
iwhen being 0, namely all B
iwith S
i(i<=m), time equal between two, court verdict o is just 1.
Wherein, result is extracted and is extracted indicator register 204 with the input termination of judgement computing circuit 205 and mould 2 adds computing circuit 203.
Wherein, the input termination external clock of counter 207, under clock signal effect, counts the number of the data cell of input shift register 201, to obtain the position of matched data in the data stream of input.
Another input end access node fruit of counter 207 is extracted and decision circuit 205, further, and if only if retrieves successfully, namely during o=1, the count value of counter 207 is stored in result cache circuit 206, represents result cache not for empty notification signal is set simultaneously.Suppose this expression result cache not for empty notification signal is oe.
Further, result cache circuit 206 allows stored in multiple result for retrieval (count value), and allows external circuit, such as processor, at any time read wherein preserve and the result for retrieval do not read.
What deserves to be explained is, if the count value direct representation need be stored in result cache circuit 206 needs retrieve data reference position in a stream, the initial value of counter 207 should be the negative of sample data length, instead of zero.Certainly, signless cycle count function still can be adopted to realize this requirement.Such as, for 16 bit counter, assuming that the length of sample data is 8, then the initial value of counter 207 should be set to 0x10000 – 0x8=0xfff8.In addition, for avoiding the output producing mistake, when circuit initializes, the radix-minus-one complement of sample data can be implanted shift register 201.
What deserves to be explained is, by the above-mentioned description to technical scheme provided by the invention, can know by inference the improvement situation done by this technical scheme.Such as, retrieve the circuit of one of multiple sample data from data stream, multiple circuit in parallel provided by the invention gets up by this circuit, allows data stream simultaneously by these circuit.And for example, the circuit of sample retrieval data from certain field of database, the workflow of this circuit to circuit provided by the invention makes the following changes: first change is, just once compares, and only once compare when the character string that is retrieved all enters shift register; Second possible change is that what type is the data that no matter are retrieved are, the width of the data cell of shift register and sample register all equals 1, and namely mould 2 adds computing and forever undertaken by bit.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is: by relatively succinct circuit, sample retrieval length the data of design load can be no more than from data stream, and the input of data, retrieval and output are synchronously carried out, i.e. retrieval and digital independent or transmitting synchronous, cost is cheaper, cost-saving.Due to simple circuit, its arithmetic speed also may faster than the circuit adopting prior art.
Embodiment 3
See Fig. 5, the embodiment of the present invention 3 provides data retrieval circuit that is a kind of and synchronization of data streams, and this circuit comprises: shift register 301, sample register 302, mould 2 add computing circuit 303, extraction indicator register 304, result extraction and decision circuit 305, result cache circuit 306, counter 307 and serial-parallel conversion circuit 308.
Wherein, shift register 301, sample register 302, mould 2 add computing circuit 303, extraction indicator register 304, result extraction and decision circuit 305, result cache circuit 306 sum counter 307, add computing circuit 203 with the shift register 201 described in the embodiment of the present invention 2, sample register 202, mould 2, extract indicator register 204, result extracts with decision circuit 205, result cache circuit 206 sum counter 207 identical, be not described in detail in this.
Wherein, the data stream of the input termination of serial-parallel conversion circuit 308 input, for be the width of serial data stream and data cell when the data stream of input be 8 or 16 time, serial data stream is changed into the parallel data stream consistent with the width of data cell; And this parallel data stream is sent into shift register 301.
Particularly, serial-parallel conversion circuit 308 meets the demand that data unit width is greater than the online retrieving being carried out the data stream transmitted while 1 by serial mode, such as, by the online retrieving of the text of Internet Transmission in a kind of comparatively simple mode.Further, the input end of serial-parallel conversion circuit 308 also for generation of the clock signal of shift register 301 and counter 302, i.e. the signal of clock 2 shown in Fig. 5.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is: by relatively succinct circuit, sample retrieval length the data of design load can be no more than from data stream, and the input of data, retrieval and output are synchronously carried out, i.e. retrieval and digital independent or transmitting synchronous, cost is cheaper, cost-saving.Due to simple circuit, its arithmetic speed also may faster than the circuit adopting prior art.
Embodiment 4
See Fig. 6 ~ Fig. 7, the embodiment of the present invention 4 provides data retrieval circuit that is a kind of and synchronization of data streams, and this circuit comprises: shift register 401, sample register 402, mould 2 add computing circuit 403, extraction indicator register 404, result extraction and decision circuit 405, result cache circuit 406, counter 407 and clock trimming circuit 408.
Wherein, shift register 401, sample register 402, mould 2 add computing circuit 403, extraction indicator register 404, result extraction and decision circuit 405, result cache circuit 406 sum counter 407, add computing circuit 203 with the shift register 201 described in the embodiment of the present invention 2, sample register 202, mould 2, extract indicator register 204, result extracts with decision circuit 205, result cache circuit 206 sum counter 207 identical, be not described in detail in this.
Wherein, clock trimming circuit 408 is constant for ensureing to maintain Counter Value during count value to result cache circuit 406 preserved by counter 407.Fig. 7 is the schematic diagram of clock trimming circuit 408 and coherent signal sequential relationship thereof.As shown in Figure 7, wherein, when result extraction and the output signal o of decision circuit 405 become high level (expression retrieves matched data), write control signal WR between counter 407 and result cache circuit 406 becomes high level from low level, performs operation counter 407 being saved in result cache register 406; Automatic returning low level after WR maintenance high level time enough.Maintain between high period at WR, clock 3 signal also will maintain high level.Like this, the dutycycle of clock signal obtains fine setting, can be buffered results and finds time.When result extract with the output signal o of decision circuit 405 be complete before negative edge that low level (show current period and do not retrieve matched data) or result cache operate in clock 1 signal arrives time, clock 3 signal is identical with clock 1.
It is emphasized that clock trimming circuit 408 is only finely tuned the dutycycle of clock signal, do not change the clock period.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is: by relatively succinct circuit, sample retrieval length the data of design load can be no more than from data stream, and the input of data, retrieval and output are synchronously carried out, i.e. retrieval and digital independent or transmitting synchronous, cost is cheaper, cost-saving.Due to simple circuit, its arithmetic speed also may faster than the circuit adopting prior art.
One of ordinary skill in the art will appreciate that all or part of step realizing above-described embodiment can have been come by hardware, the hardware that also can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium mentioned can be ROM (read-only memory), disk or CD etc.
The foregoing is only preferred embodiment of the present invention; not in order to limit the present invention; within the spirit and principles in the present invention all, any combination done, sub-portfolio, reduction, amendment, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1., with the data retrieval circuit of synchronization of data streams, it is characterized in that, described circuit comprises:
Shift register, under clock signal effect, each clock period receives a data cell in input traffic, the data mobile simultaneously deposited previous clock period data cell;
Sample register, for pre-setting sample data, described sample data comprises some data cells; Described shift register is identical with described sample register length; And the length of described sample data is less than or equal to the length of described sample register;
Mould 2 adds computing circuit, adds computing for the data in the data in described shift register and described sample register are carried out mould 2;
Extract indicator register, be used to indicate described mould 2 and add significance bit part in the operation result of computing;
Result is extracted and decision circuit, adds significance bit part in the operation result of computing for extracting described mould 2; And whether retrieve the data consistent with described sample data according to described significance bit part judgement; If judgement for retrieving the data consistent with described sample data, then produces matched signal;
Wherein, described mould 2 add computing circuit specifically for,
Data cell corresponding in data cell in described shift register and described sample register is carried out mould 2 respectively and adds computing; I-th data cell corresponding in i-th data cell of data in described shift register and described sample register is carried out mould 2 to add computing and be,
M
i＝B
i⊕S
i＝(b
i0⊕s
i0)∨(b
i1⊕s
i1)∨……∨(b
i(N-1)⊕s
i(N-1))
Wherein, B
ifor i-th data cell of data in described shift register, S
ifor i-th data cell in described sample register, N is the width of described data cell, b
ijwith s
ijbe respectively described B
iwith described S
ia middle jth bit; M
ifor i-th data cell corresponding in i-th data cell of data in described shift register and described sample register being carried out the operation result that mould 2 adds computing, M
ibe specially boolean's data of a bit.
2. circuit as claimed in claim 1, it is characterized in that, the width size of described data cell is 1,8 or 16.
3. circuit as claimed in claim 1, is characterized in that, described extraction indicator register specifically for,
Pre-set the designation data that the described mould 2 of instruction adds the live part of the operation result of computing; Described designation data is,
Wherein, the length of described sample data is m+1, and the length of described shift register is n+1, and m≤n; f
ifor i-th Bit data of described designation data.
4. circuit as claimed in claim 3, is characterized in that, described result extract with decision circuit specifically for,
The data described mould 2 being added corresponding position in the operation result of computing and described designation data are carried out and computing respectively, extract described mould 2 and add significance bit part in the operation result of computing; Described mould 2 is added the i-th corresponding bit data in the operation result of computing and described designation data carry out with computing be,
C
i＝M
if
i
Carry out described or non-computational with each data in the operation result of computing, judge whether to retrieve the data consistent with described sample data according to operation result that is described or non-computational; Described or non-computational is,
Wherein, M
ifor i-th data cell corresponding in i-th data cell of data in described shift register and described sample register being carried out the operation result that mould 2 adds computing; C
ithe operation result with computing is carried out for described mould 2 being added the i-th corresponding bit data in the operation result of computing and described designation data; C
0, C
1..., C
m, C
m+1..., C
nbe respectively described with the operation result of computing in the 0th, 1 ..., m, m+1 ..., n-bit data; O is operation result that is described or non-computational;
As o=1, be judged as retrieving the data consistent with described sample data, produce matched signal;
As o=0, be judged as not retrieving the data consistent with described sample data, produce mismatch signal.
5. circuit as claimed in claim 1, it is characterized in that, described circuit also comprises counter and result cache circuit,
Described counter is used for, and counts the number of the data cell inputting described shift register,
Correspondingly, described result cache circuit is used for, when described result is extracted and decision circuit produces matched signal, and the current count value of counter described in buffer memory.
6. circuit as claimed in claim 1, it is characterized in that, described circuit also comprises serial-parallel conversion circuit,
Described serial-parallel conversion circuit is used for, when described input traffic be serial data stream and the width of described data cell be 8 or 16 time, described serial data stream is changed into the parallel data stream consistent with the width of described data cell; And described parallel data stream is sent into described shift register.
7. circuit as claimed in claim 5, it is characterized in that, described circuit also comprises clock trimming circuit,
Described clock trimming circuit is used for, and maintains described clock signal state constant during the current count value preserving described counter.
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| CN103744827A (en) * | 2014-01-10 | 2014-04-23 | 浪潮电子信息产业股份有限公司 | Serial data frame matching method for improving chip logical time sequence |
| CN104331467B (en) * | 2014-10-31 | 2019-02-26 | 上海玮舟微电子科技有限公司 | A kind of data query method and system |
| CN105512310A (en) * | 2015-12-11 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | Data precise and fuzzy search method based on FC-AE-ASM (Fiber Channel-Avionics Environment-Anonymous Subscriber Message) protocol |
| CN105553545A (en) * | 2015-12-11 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | FC data acquisition and recording instrument recording condition control strategy |
| CN106201440B (en) * | 2016-06-28 | 2018-10-23 | 上海兆芯集成电路有限公司 | The central processing unit of character string comparison optimization and its operating method |
| CN106776394B (en) * | 2017-01-11 | 2019-05-14 | 深圳大普微电子科技有限公司 | A kind of hardware system and memory of data conversion |
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| JPS58134336A (en) * | 1982-02-03 | 1983-08-10 | Ricoh Co Ltd | Word searching device |
| JPS592142A (en) * | 1982-06-29 | 1984-01-07 | Fujitsu Ltd | Bit train retrieving system |
| JPH0833896B2 (en) * | 1987-02-23 | 1996-03-29 | 株式会社日立製作所 | Failure detection method for character string retrieval device |
| JP3316882B2 (en) * | 1992-08-27 | 2002-08-19 | 安藤電気株式会社 | Pattern match / mismatch detection circuit |
| JPH0981367A (en) * | 1995-09-14 | 1997-03-28 | Mitsubishi Electric Corp | Pattern detection circuit |
| JPH0991119A (en) * | 1995-09-21 | 1997-04-04 | Matsushita Electric Works Ltd | Matching detection circuit |
| JP2006162645A (en) * | 2004-12-02 | 2006-06-22 | Oki Electric Ind Co Ltd | Liquid crystal driving circuit, liquid crystal display device and boost frequency control method |
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