CN103744827A - Serial data frame matching method for improving chip logical time sequence - Google Patents
Serial data frame matching method for improving chip logical time sequence Download PDFInfo
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- CN103744827A CN103744827A CN201410011293.3A CN201410011293A CN103744827A CN 103744827 A CN103744827 A CN 103744827A CN 201410011293 A CN201410011293 A CN 201410011293A CN 103744827 A CN103744827 A CN 103744827A
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Abstract
The invention discloses a serial data frame matching method for improving a chip logical time sequence. A baseline offset shifter, a normal data frame comparator, a multi-dimension matching grouping structure and a matching integrated positioning controller are arranged in a serial data processing module, firstly, serial data are input to the baseline offset shifter to shift and slide in the baseline offset shifter and then compared with normal data frames in the normal data frame comparator, later, a matching result is output, the matching result includes hit information, the matching result is subjected to multi-dimension grouping and logical processing in the multi-dimension matching grouping structure, matching information subjected to the logical processing is subjected to recombination by the matching integrated positioning controller to form control signals for positioning and matching data, and the data can be rapidly positioned and matched, and cached and output. Compared with serial data frame matching methods in prior art, the serial data frame matching method has the advantages that the complexity of the logical design of serial data processing is greatly reduced, and the chip logical time sequence is effectively improved.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, specifically a kind of serial data frame matching process that improves chip logic sequential.
Background technology
Along with the develop rapidly of computer technology and integrated circuit technique, high performance computer system more and more becomes the needs of socio-economic development.This has brought design challenge with regard to fields such as the core frequency for computer system key chip group, data transfer bandwidth, high speed transmission of signals.Key chip group core frequency reaches GHz at present, and data transfer bandwidth reaches tens GB/s, high speed transmission of signals rate 10Gbps left and right.Therefore this is just for serial data high-speed transfer design in sheet brings huge difficult problem.The serial data processing logic complex structure of high-bit width on the one hand, huge processing logic cannot meet the requirement of chip high-frequency sequential; The data transmission of high speed makes the detection difficulty of matching of Frame very big on the other hand, deals with improperly and still can make the logical sequence of chip reduce, and cannot meet the designing requirement of high-frequency, high bandwidth.
summary of the invention
Technical assignment of the present invention is to provide a kind of serial data frame matching process that improves chip logic sequential.
Technical assignment of the present invention is realized in the following manner, the method step is as follows: datum offset shift unit, normal data frame comparer, various dimensions matched packet structure and coupling integrated positioning controller are set in serial data processing module inside, first by serial data input reference skew shift unit, the serial data slip that is shifted in datum offset shift unit, then in normal data frame comparer, compare with normal data frame, output matching result afterwards, comprises one and hits information in this matching result; Then this matching result carried out in various dimensions matched packet structure to various dimensions grouping and carry out logical process, match information through logical process reconfigures the control signal that forms position matching data through overmatching integrated positioning controller, the output of position matching data, and buffer memory fast.
Described datum offset shift unit designs three groups of impact dampers, be respectively impact damper Buffer1, impact damper Buffer2 and impact damper Buffer3, the width of impact damper is consistent with input data bit width, and take impact damper Buffer2 as benchmark, carries out left and right sidesing shifting during shift control.
At data sending terminal encapsulation normal data frame, the data after displacement are compared at normal data frame comparer and normal data frame, according to the settle the standard bit wide of Frame comparer Data Matching result of the figure place of datum offset shift unit data left and right sidesing shifting.
In various dimensions matched packet structure, adopt the mode of position grouping continuously and the position grouping of jumping, realize respectively the horizontal grouping of normal data frame comparer Data Matching result and longitudinally grouping.
The matching result of laterally grouping and longitudinally grouping is combined, for controlling the accurate location of matched data, and export after buffer memory.
Compared to the prior art a kind of serial data frame matching process that improves chip logic sequential of the present invention, has following beneficial effect:
The characteristic of datum offset shift unit, mainly refer in serial data Frame control module and design 3 groups of impact dampers (Buffer), in order to realize input data shift control, the width of Buffer is consistent with input data bit width, and during shift control, take Buffer2 as benchmark, carry out left and right sidesing shifting, according to the actual transmissions situation capable of regulating displacement width of link, reduce design complexities, improve sequential; The characteristic of various dimensions matched packet structure, the result that mainly refers to comparer comparison match is carried out respectively horizontal and vertical grouping according to continuous position and the position of jumping, continuously the granularity of position and the position of jumping can be determined according to the data width that is shifted, if displacement width is larger, can be take n/4 or n/8 as granularity, if displacement width is less, can be take n as granularity, n is displacement width, can effectively reduce like this complexity and the logic scale of high-bit width data processing, improves chip logic sequential; The characteristic of coupling integrated positioning controller, mainly refers to that grouping control signal after treatment, through reconfiguring, forms the positioning control signal of matched data, the output of position matching data, and buffer memory fast.The above-mentioned advantage that the serial data frame adaptation design method of this raising chip logic sequential has, make it make up the complicated huge deficiency of high-bit width serial data processing logic, adopt grouping steering logic to process and substitute high-bit width original data processing, greatly reduce the complexity of serial data processing logic design, effectively improved chip logic sequential, no matter in fpga chip logical design, or in asic chip logical design, all there is very high technological value.
Accompanying drawing explanation
Accompanying drawing 1 is the structural representation of serial data frame coupling;
Accompanying drawing 2 is the structural representation of datum offset shift unit;
Accompanying drawing 3 is the schematic diagram of various dimensions matched packet structure.
In figure: 1, datum offset shift unit, 2, normal data frame comparer, 3, various dimensions matched packet structure, 4, coupling integrated positioning controller.
Embodiment
Embodiment 1:
The serial data DATA_IN of 32 is input reference skew shift unit 1 first, this datum offset shift unit 1 designs three groups of impact dampers, be respectively impact damper Buffer1, impact damper Buffer2 and impact damper Buffer3, 32 bit data are at transmitting terminal encapsulation normal data frame, the normal data frame that DATA_IN comprises will be at impact damper Buffer1, impact damper Buffer2 and the impact damper Buffer3 slip that is shifted, the width that displacement is slided take impact damper Buffer2 as origin reference location data, maximum 64 bit shifts of supporting, minimum 0 bit shift of supporting, factor data bit wide position 32, under general condition, data displacement can not exceed 32, according to the actual transmissions situation of link, can dwindle or increase this displacement width.Suppose that displacement width is 32,32 shifted data are compared with normal data frame in normal data frame comparer 2, export the matching result (R) of 32, in this matching result, comprise one and hit information.
The matching result of 32 is carried out to various dimensions grouping according to the granularity of n/4 or n/8 in various dimensions matched packet structure 3, as being laterally divided into 8 groups, longitudinally be divided into 4 groups, horizontal and vertical grouping information is carried out to logical process, and laterally longitudinally information combination processing of final realization, because of grouping after signal simple, only comprise one and hit information, and bit wide is less, so the efficiency of multi-set parallel processing is high, can effectively improve the logical sequence of this part, solve whole chip high-bit width serial data and process the low design bottleneck of sequential, match information through logical process reconfigures the control signal that forms position matching data through overmatching integrated positioning controller 4, position matching data fast, and buffer memory output.
Claims (5)
1. one kind is improved the serial data frame matching process of chip logic sequential, it is characterized in that, datum offset shift unit, normal data frame comparer, various dimensions matched packet structure and coupling integrated positioning controller are set in serial data processing module inside, first by serial data input reference skew shift unit, the serial data slip that is shifted in datum offset shift unit, then in normal data frame comparer, compare with normal data frame, output matching result afterwards, comprises one and hits information in this matching result; Then this matching result carried out in various dimensions matched packet structure to various dimensions grouping and carry out logical process, match information through logical process reconfigures the control signal that forms position matching data through overmatching integrated positioning controller, the output of position matching data, and buffer memory fast.
2. a kind of serial data frame matching process that improves chip logic sequential according to claim 1, it is characterized in that, described datum offset shift unit designs three groups of impact dampers, be respectively impact damper Buffer1, impact damper Buffer2 and impact damper Buffer3, the width of impact damper is consistent with input data bit width, and take impact damper Buffer2 as benchmark, carries out left and right sidesing shifting during shift control.
3. a kind of serial data frame matching process that improves chip logic sequential according to claim 1, it is characterized in that, at data sending terminal encapsulation normal data frame, data after displacement are compared at normal data frame comparer and normal data frame, according to the settle the standard bit wide of Frame comparer Data Matching result of the figure place of datum offset shift unit data left and right sidesing shifting.
4. a kind of serial data frame matching process that improves chip logic sequential according to claim 1, it is characterized in that, in various dimensions matched packet structure, adopt the mode of position grouping continuously and the position grouping of jumping, realize respectively the horizontal grouping of normal data frame comparer Data Matching result and longitudinally grouping.
5. a kind of serial data frame matching process that improves chip logic sequential according to claim 4, is characterized in that, the matching result of laterally grouping and longitudinally grouping is combined, and for controlling the accurate location of matched data, and exports after buffer memory.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105512310A (en) * | 2015-12-11 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | Data precise and fuzzy search method based on FC-AE-ASM (Fiber Channel-Avionics Environment-Anonymous Subscriber Message) protocol |
| CN105553545A (en) * | 2015-12-11 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | FC data acquisition and recording instrument recording condition control strategy |
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| US20100103929A1 (en) * | 2008-10-29 | 2010-04-29 | Seung-Jong Lee | Method, apparatus, and system for automatic data aligner for multiple serial receivers |
| CN102708080A (en) * | 2012-04-20 | 2012-10-03 | 浪潮(北京)电子信息产业有限公司 | Method and system for aligning high speed serial communication channels |
| CN102736888A (en) * | 2012-07-02 | 2012-10-17 | 江汉大学 | Data retrieval circuit being synchronous with data stream |
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- 2014-01-10 CN CN201410011293.3A patent/CN103744827A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1281297A (en) * | 1999-07-19 | 2001-01-24 | 深圳市华为技术有限公司 | Method for synchronizing psuedo-random sequences in linear band spreading system |
| US20100103929A1 (en) * | 2008-10-29 | 2010-04-29 | Seung-Jong Lee | Method, apparatus, and system for automatic data aligner for multiple serial receivers |
| CN102708080A (en) * | 2012-04-20 | 2012-10-03 | 浪潮(北京)电子信息产业有限公司 | Method and system for aligning high speed serial communication channels |
| CN102736888A (en) * | 2012-07-02 | 2012-10-17 | 江汉大学 | Data retrieval circuit being synchronous with data stream |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105512310A (en) * | 2015-12-11 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | Data precise and fuzzy search method based on FC-AE-ASM (Fiber Channel-Avionics Environment-Anonymous Subscriber Message) protocol |
| CN105553545A (en) * | 2015-12-11 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | FC data acquisition and recording instrument recording condition control strategy |
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