JPS6279626A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6279626A JPS6279626A JP22063585A JP22063585A JPS6279626A JP S6279626 A JPS6279626 A JP S6279626A JP 22063585 A JP22063585 A JP 22063585A JP 22063585 A JP22063585 A JP 22063585A JP S6279626 A JPS6279626 A JP S6279626A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- cvd
- temperature
- insulation film
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造方法における半導体基板上
に形成された凹凸パターンの表面を平坦第2図A、Bは
従来の表面平坦化方法の主要段階における状態を示す断
面図である。第2図において、半導体基板(1)上に凹
凸パターン(2)が形成されたままの状態ではその上に
直接アルミニウム(Al)配線を形成すると、凹凸のエ
ツジが急峻であるので、そのA6配線に断線を生じ易い
などの問題がち9、これを回避するために表面の平坦化
が従来から行なわれている。すなわち、まず、第2図A
に示すように、凹凸パターン(2)が形成さ几、かつ、
内部に不純物の導入領域(3)を有する半導体基板(1
)の上にO’VD法でリフローの可能な絶線物〔例えば
、リンガラス(pso) 、ボロンリンガラス(BPS
G)等〕の膜(4)を成膜し、その後、第2図Bに示す
ように熱処理によって絶縁膜(4)をリフローさせて表
面の平坦化を達成していた。[Detailed Description of the Invention] [Industrial Application Field] This invention is a method for manufacturing semiconductor devices, in which the surface of a concavo-convex pattern formed on a semiconductor substrate is flattened. FIG. 3 is a sectional view showing a state at a main stage. In FIG. 2, when the uneven pattern (2) is still formed on the semiconductor substrate (1), if aluminum (Al) wiring is formed directly on it, the edges of the unevenness will be steep, so the A6 wiring However, in order to avoid this problem, flattening of the surface has been conventionally performed. That is, first, Figure 2A
As shown in the figure, the uneven pattern (2) is formed, and
A semiconductor substrate (1) having an impurity introduced region (3) therein.
), which can be reflowed using the O'VD method [e.g., phosphorus glass (PSO), boron phosphorus glass (BPS)
After that, as shown in FIG. 2B, the insulating film (4) was reflowed by heat treatment to achieve surface planarization.
従来の方法では凹凸パターン(2)を有する半導体基板
(1)の凹凸表面の平坦化のためにリフロー可能な絶縁
膜(4)をその凹凸面上形成し、これを高温でリフロー
させていたが、このときの必要な1000℃に近い温度
での処理では、第2図Bにも示したように不純物導入領
域(3)の不純物の再拡散を生じ、半導体素子の微細化
に支障となるという問題点があった。In the conventional method, in order to flatten the uneven surface of a semiconductor substrate (1) having an uneven pattern (2), a reflowable insulating film (4) is formed on the uneven surface and this is reflowed at a high temperature. At this time, the required treatment at a temperature close to 1,000°C causes re-diffusion of impurities in the impurity-introduced region (3), as shown in Figure 2B, which hinders the miniaturization of semiconductor devices. There was a problem.
この発明は以上のような問題点を解消するためになされ
たもので、不純物の再拡散を生ずることなく表面を平坦
化できる方法を得ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide a method that can flatten the surface without causing impurity re-diffusion.
この発明に係る半導体装置の製造方法では、半導体基板
内の不純物の再拡散が生じない程度の温度で絶縁膜をC
VD成膜させるとともにそのcvp装置のパワーを増大
させて絶縁膜のリフローも同時に行わしめるものである
。In the method for manufacturing a semiconductor device according to the present invention, the insulating film is heated to a temperature that does not cause re-diffusion of impurities in the semiconductor substrate.
In addition to VD film formation, the power of the CVP equipment is increased to perform reflow of the insulating film at the same time.
この発明ではcvp*tのパワーを大きくすることによ
って絶縁膜の成膜と同時に低温でリフローζせることが
できる。In this invention, by increasing the power of cvp*t, reflow ζ can be performed at a low temperature simultaneously with the formation of an insulating film.
第1図はこの発明の一実施例の方法で表面を平坦化した
半導体基体を示す断面図で、従来例と同一符号は同等部
分を示す。表面に凹凸パターン(2)を有する半導体基
板(1)をCVD用チャンバー(図示せず)内に収容し
プラズマCVDによって800’C前後の温度で絶縁膜
(4)を成膜させるが、このとき、このCVD装置のパ
ワーを増大してやると、スパッタリング効果が現れ、図
示のように、リフローが達成できる。FIG. 1 is a sectional view showing a semiconductor substrate whose surface has been planarized by a method according to an embodiment of the present invention, and the same reference numerals as in the conventional example indicate equivalent parts. A semiconductor substrate (1) having an uneven pattern (2) on its surface is housed in a CVD chamber (not shown), and an insulating film (4) is formed by plasma CVD at a temperature of about 800'C. When the power of this CVD apparatus is increased, a sputtering effect appears and reflow can be achieved as shown in the figure.
上記実施例では、金属配線の断線防止のための下地平坦
化を取り上げたが、三次元素子などの配線間の段差が大
きなものについても適用できる0〔発明の効果〕
以上のように、この発明ではプラズマOVDのパワーを
大きくすることによって、凹凸パターンを有する半導体
基板上に絶縁膜の成膜と同時に低温で曇i母その絶縁膜
のリフローが可能であるので、上記半導体基板内に導入
されている不純物の再分布を生ずることすく、微細化プ
ロセスに好適である0Although the above embodiment deals with flattening the base to prevent disconnection of metal wiring, it can also be applied to devices with large steps between wiring such as tertiary elements.0 [Effects of the Invention] As described above, this invention By increasing the power of plasma OVD, it is possible to form an insulating film on a semiconductor substrate having an uneven pattern and simultaneously reflow the insulating film at a low temperature. 0, which is suitable for the miniaturization process because it does not cause redistribution of impurities.
第1図はこの発明の一実施例の方法で表面を平坦化され
た半導体基体を示す断面図、第2図A。
Bは従来の表面平坦化方法の主要段階における状態を示
す断面図である。
図において、(1)は半導体基板、(2)は凹凸パター
ン、(3)は不純物導入領域、(4)は絶縁膜である。
なお、図中同一符号は同一または相当部分を示す。FIG. 1 is a cross-sectional view showing a semiconductor substrate whose surface has been planarized by a method according to an embodiment of the present invention, and FIG. 2A. B is a cross-sectional view showing the main stages of a conventional surface flattening method. In the figure, (1) is a semiconductor substrate, (2) is an uneven pattern, (3) is an impurity introduced region, and (4) is an insulating film. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (2)
マCVD装置のチャンバー内に収容して低温で上記凹凸
パターン上に低温で絶縁膜を形成させるとともに上記プ
ラズマCVD装置のパワーを増大させて上記低温の状態
で上記絶縁膜のリフローを同時に行なわせる工程を備え
た半導体装置の製造方法。(1) A semiconductor substrate having an uneven pattern on its surface is housed in a chamber of a plasma CVD apparatus, and an insulating film is formed at a low temperature on the uneven pattern at a low temperature, and the power of the plasma CVD apparatus is increased to A method for manufacturing a semiconductor device, comprising a step of simultaneously performing reflow of the insulating film in the state.
ローを行なう温度は半導体基体内に導入されている不純
物の再分布の温度より低くすることを特徴する特許請求
の範囲第1項記載の半導体装置の製造方法。(2) The semiconductor device according to claim 1, wherein the temperature at which the insulating film is formed and reflowed using a plasma CVD apparatus is lower than the temperature at which impurities introduced into the semiconductor substrate are redistributed. manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22063585A JPS6279626A (en) | 1985-10-03 | 1985-10-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22063585A JPS6279626A (en) | 1985-10-03 | 1985-10-03 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6279626A true JPS6279626A (en) | 1987-04-13 |
Family
ID=16754059
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22063585A Pending JPS6279626A (en) | 1985-10-03 | 1985-10-03 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6279626A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11040654B2 (en) | 2019-03-29 | 2021-06-22 | Honda Motor Co., Ltd. | Control apparatus |
-
1985
- 1985-10-03 JP JP22063585A patent/JPS6279626A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11040654B2 (en) | 2019-03-29 | 2021-06-22 | Honda Motor Co., Ltd. | Control apparatus |
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