JPS62174947A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62174947A JPS62174947A JP1846486A JP1846486A JPS62174947A JP S62174947 A JPS62174947 A JP S62174947A JP 1846486 A JP1846486 A JP 1846486A JP 1846486 A JP1846486 A JP 1846486A JP S62174947 A JPS62174947 A JP S62174947A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- interconnections
- hillocks
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000012298 atmosphere Substances 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005260 corrosion Methods 0.000 abstract description 3
- 230000007797 corrosion Effects 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
この発明は半導体装置の製造方法に関し、特にアルミニ
ウム配線におけるアルミニウムヒロックの発生の防止に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a method for manufacturing a semiconductor device, and particularly to prevention of aluminum hillocks in aluminum wiring.
［従来の技１ｆｉ ］
第２Ａ図〜第２ Ｆ Ｌ＝ｉ ＬＬ、従来の半導体装置
の製造方法の主要工程段階における状態を示すＩＩ而面
である。この製造方法について説明すると、まず、シリ
コン基板１上に熱酸化法などで下？２酸化ｌｌ！ｌ ２
を形成する（第２Ａ図）。次に、下敷酸化膜２上にスパ
ッタ法などでアルミニウム配線１１ＪＩ３を形成する（
第２Ｂ図）。次に、アルミニウム配置［３上にフォトレ
ジストを塗布し、これを写輿製版してフォトレジスト膜
パターン４ａを形成する（第２Ｃ図）。次に、フォトレ
ジスト膜パターン４ａをマスクとして、アルミニウム配
線膜３を乾式および湿式でエツチングしてアルミニウム
配線３ａを形成する（第２Ｄ図）。次に、アルミニウム
♂己線３ａの電気抵抗を減らし、その電気的な接触の安
定を図るために、アルミニウム配置３ａを４００〜５０
０℃程度でかつ常圧のＮ２またはＮ２雰囲気中で熱ｆｆ
１ｌｕするが、このとき、アルミニウムグレインの再結
晶化により、アルミニウム配Ｐｉ１３ａにアルミニウム
ヒロック５が発生する（第２Ｅ図）３次に、下敷酸１ヒ
膜２上およびアルミニウム配置３ａ上にＣＶＤ法により
Ｐ Ｓ Ｇ （Ｐ ｈｏｓｐｈ。[Conventional Technique 1fi] FIGS. 2A to 2F L=i LL are planes II showing states at main process steps of a conventional semiconductor device manufacturing method. To explain this manufacturing method, first, silicon substrate 1 is coated with heat oxidation method or the like. Dioxide ll! l 2
(Figure 2A). Next, aluminum wiring 11JI3 is formed on the underlying oxide film 2 by sputtering or the like (
Figure 2B). Next, a photoresist is applied onto the aluminum arrangement [3] and photoresist is applied to form a photoresist film pattern 4a (FIG. 2C). Next, using the photoresist film pattern 4a as a mask, the aluminum wiring film 3 is dry- and wet-etched to form an aluminum wiring 3a (FIG. 2D). Next, in order to reduce the electrical resistance of the aluminum ♂ self-wire 3a and stabilize the electrical contact, the aluminum arrangement 3a is
Heat ff in N2 or N2 atmosphere at around 0℃ and normal pressure
1lu, but at this time, aluminum hillocks 5 are generated on the aluminum arrangement Pi 13a due to recrystallization of the aluminum grains (Fig. 2E). P S G (P hosph.
３ ＋＋１ｃａｔｅ Ｑ １ａｓｓ）やＢ Ｐ Ｓ Ｇ
（Ｂ ｏｒｏ Ｐ ｌｏｓ＋）ｈ。3 ++1cate Q 1ass) and B P S G
(B oro P los+)h.
３１ｌｉｃａｔｅ Ｑ １ａｓｓ）などの＄８縁表面保
護ｌＩ６を形成するが、このとき、アルミニウムヒロッ
ク５は絶縁表面保護膜６で完全に覆われない（第２Ｆ図
）。31licate Q 1ass), but at this time, the aluminum hillock 5 is not completely covered with the insulating surface protection film 6 (FIG. 2F).
［発明が解決しようとする問題点コ
従来の半導体装置は以上のような工程で製造されるが、
アルミニウム配置３ａにアルミニウムヒロック５が発生
し、アルミニウムヒロック５が絶縁表面床′ｓ１６で完
全に覆われないためアルミニウム腐蝕の原因となったり
、またアルミニウム上０ツク同士の接触によりアルミニ
ウム配線３ａ間にショートが起こるという問題点があっ
た。[Problems to be solved by the invention: Conventional semiconductor devices are manufactured through the steps described above, but
Aluminum hillocks 5 occur in the aluminum arrangement 3a, and the aluminum hillocks 5 are not completely covered with the insulating surface floor's16, causing aluminum corrosion, and short circuits between the aluminum wiring 3a due to contact between aluminum wires 3a. There was a problem that this occurred.
この発明は上記のような問題点を解消するためになされ
たもので、アルミニウム配線にアルミニウムヒロックが
発生するのを防止することができる半導体装置の製造方
法を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent aluminum hillocks from occurring in aluminum wiring.
し問題点を解決するための手段〕
この発明に係る半導体装置の製造方法は、アルミニウム
配線の熱処理をアルミニウム配線に高圧力をかけながら
行なう方法である。Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention is a method in which heat treatment of aluminum wiring is performed while applying high pressure to the aluminum wiring.
［作用］
この発明に６３いては、アルミニウム配線の熱処理をア
ルミニウム配線に高圧力をかけなからｔテなうので、ア
ルミニウム配線にアルミニウムヒロックが発生しない。[Function] According to the present invention, since the aluminum wiring is heat-treated without applying high pressure to the aluminum wiring, aluminum hillocks do not occur in the aluminum wiring.
〔実施例］ 以下、この発明の実施例を図について説明する。〔Example] Embodiments of the present invention will be described below with reference to the drawings.
なお、この実施例の説明において、従来の技（イｉの説
明と重複する部分については適宜その説明を省略する。In the description of this embodiment, the description of parts that overlap with the description of the conventional technique (i) will be omitted as appropriate.
第１Ａ図〜第１Ｆ図は、この発明の実施例である半導体
装置の製造方法の主要工程段階における状態を示す断面
図である。この製造方法について説明すると、第１Ａ図
から第１Ｄ図までの工程は、従来の半導体装置の製造方
法の工程と同じである。1A to 1F are cross-sectional views showing the main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. To explain this manufacturing method, the steps from FIG. 1A to FIG. 1D are the same as those of a conventional semiconductor device manufacturing method.
第１Ｄ図の工程を経た後、アルミニウム配線３ａを４０
０〜５００℃程度でかつ５気圧以上の高圧力のＮ２また
はＨ２雰囲気中で熱処理する。このとき、アルミニウム
ヒロックが発生する力よりも高圧力による圧縮力の方が
大きいため、アルミニウムｌＩ’ｉ！ｌ１１３ａにはア
ルミニウムヒロックが発生しない（第１Ｅ図）。次に、
下敷酸化膜２上およびアルミニウム配置３ａ上にＣＶＤ
法によりＰＳＧやＢＰＳＧなどの絶縁表面保護膜６を形
成する（第１Ｆ図）。After going through the process shown in Figure 1D, the aluminum wiring 3a is
Heat treatment is performed in an N2 or H2 atmosphere at a temperature of about 0 to 500°C and a high pressure of 5 atm or more. At this time, the compressive force due to the high pressure is greater than the force generated by the aluminum hillock, so the aluminum lI'i! No aluminum hillocks occur in l113a (Fig. 1E). next,
CVD on the underlying oxide film 2 and the aluminum arrangement 3a
An insulating surface protection film 6 such as PSG or BPSG is formed by a method (FIG. 1F).
なお、上記実施例では、アルミニウム配Ｉｔ！３ａの熱
処理を高圧力下で行なう場合について示したが、アルミ
ニウム配線３ａ １．ＪＦｊ重をかけながらこの熱処理
を行なうようにしてもよい。In addition, in the above embodiment, the aluminum wiring It! Although the case where the heat treatment of 3a is performed under high pressure has been shown, aluminum wiring 3a 1. This heat treatment may be performed while applying a JFj weight.
［発明の効果〕
以上のようにこの発明によれば、アルミニウム配線の熱
処理をアルミニウム配線に高圧力をかけながら行なうよ
うにしたので、アルミニウムｌ！ｉ！１１ニアルミニウ
ムヒロックが発生するのを防止することができる半導体
装置の製造方法を得ることができる。このため、アルミ
ニウムヒロックによるアルミニウム腐蝕、アルミニウム
配線間のショートをなくすことができる。[Effects of the Invention] As described above, according to the present invention, the heat treatment of the aluminum wiring is performed while applying high pressure to the aluminum wiring, so that the aluminum l! i! A method for manufacturing a semiconductor device that can prevent the occurrence of 11-nia aluminum hillocks can be obtained. Therefore, aluminum corrosion caused by aluminum hillocks and short circuits between aluminum wirings can be eliminated.
第ＩＡ図〜？ＡＩＦ図は、この弁明の実施例である半導
体装置のＷＩＪ造方決方法要工程段階における状態を示
プ断面図である。
第２Ａ図〜第２Ｆ図は、従来の半導体装置の製造方法の
主要工程段階にあける状態を示す断面図である。
１はシリコン基板、２は下！２酸化膜、３はアルミニウ
ムｌｌｉ！ ａ 膜、３ａはアルミニウム配線、４ａは
フォトレジスｔ− Ｓパターン、５はアルミニウムヒロ
ック、６は絶縁表面像ｍ脱である。
なお、各図中同一符号は同一または相当部分を示す。Figure IA~? The AIF diagram is a cross-sectional view showing the state at the essential process steps of the WIJ manufacturing method for a semiconductor device, which is an embodiment of this explanation. FIGS. 2A to 2F are cross-sectional views showing main process steps of a conventional method for manufacturing a semiconductor device. 1 is the silicon substrate, 2 is the bottom! Dioxide film, 3 is aluminum lli! 3a is a film, 3a is an aluminum wiring, 4a is a photoresist t-S pattern, 5 is an aluminum hillock, and 6 is an insulating surface image. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (2)
処理を、該アルミニウム配線に高圧力をかけながら行な
うことを特徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device, characterized in that heat treatment of aluminum wiring formed on a semiconductor substrate is performed while applying high pressure to the aluminum wiring.
囲気中で行なうことによつて前記アルミニウム配線に高
圧力をかける特許請求の範囲第１項記載の半導体装置の
製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed in an N_2 or H_2 atmosphere of 5 atmospheres or more, thereby applying high pressure to the aluminum wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1846486A JPS62174947A (en) | 1986-01-28 | 1986-01-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1846486A JPS62174947A (en) | 1986-01-28 | 1986-01-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62174947A true JPS62174947A (en) | 1987-07-31 |
Family
ID=11972355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1846486A Pending JPS62174947A (en) | 1986-01-28 | 1986-01-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62174947A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03222332A (en) * | 1990-01-26 | 1991-10-01 | Fujitsu Ltd | Manufacture of semiconductor device |
| US6194311B1 (en) | 1998-06-26 | 2001-02-27 | Nec Corporation | Method for manufacturing semiconductor device capable of effectively carrying out hydrogen passivation |
-
1986
- 1986-01-28 JP JP1846486A patent/JPS62174947A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03222332A (en) * | 1990-01-26 | 1991-10-01 | Fujitsu Ltd | Manufacture of semiconductor device |
| US6194311B1 (en) | 1998-06-26 | 2001-02-27 | Nec Corporation | Method for manufacturing semiconductor device capable of effectively carrying out hydrogen passivation |
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