JPS6278852A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6278852A
JPS6278852A JP21836285A JP21836285A JPS6278852A JP S6278852 A JPS6278852 A JP S6278852A JP 21836285 A JP21836285 A JP 21836285A JP 21836285 A JP21836285 A JP 21836285A JP S6278852 A JPS6278852 A JP S6278852A
Authority
JP
Japan
Prior art keywords
film
oxide film
silicon oxide
silicon
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21836285A
Other languages
Japanese (ja)
Other versions
JPH0799745B2 (en
Inventor
Shozo Nishimoto
西本 昭三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60218362A priority Critical patent/JPH0799745B2/en
Publication of JPS6278852A publication Critical patent/JPS6278852A/en
Publication of JPH0799745B2 publication Critical patent/JPH0799745B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To obtain an insulating film suitable for flattening and microminiaturization of an element by a method wherein the polysilicon film being in contact with the side surface of the lower conductive film pattern is entirely changed into a silicon oxide film and the upper conductive film insulated from the lower conductive film is provided through the oxide film of the lower conductive film. CONSTITUTION:The region other than the desired region of a three layer film is etched away by a photo etching method and a polysilicon film 6 is deposited on the whole surface. The polysilicon film 6 is entirely changed into a silicon oxide film 7 by a thermal oxidation method, a thermal oxidation is continued and the side surface of a polysilicon film 3 is oxidized. The whole surface being etched away, a silicon oxide film 2 being in contact with silicon substrate 1 and the silicon oxide film 7 are all etched away and the etching is stopped in the state that the silicon oxide film 7 is left on the side surface of the polysilicon film 3. A silicon oxide film 8 is formed on the exposed surface of the substrate 1 in the desired thickness and a polysilicon film 9 is deposited as the upper conductive layer.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に導電層間の
絶縁膜の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an insulating film between conductive layers.

〔従来の技術〕[Conventional technology]

従来、導電f−間に絶縁膜を形成するには、下層の導電
層表面に熱酸化法により絶縁膜を形成し、その上に上層
の導電層を形成していた。
Conventionally, in order to form an insulating film between conductive layers, an insulating film is formed on the surface of a lower conductive layer by a thermal oxidation method, and an upper conductive layer is formed thereon.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の絶縁膜の形成方法は、工程数は少いもの
の、均一な膜厚の絶縁膜を得るのが大変難しく、特に絶
縁膜上に設け、所定形状に加工した下層の導電層の端部
の側壁で絶縁膜の膜厚が薄くなり、下地の絶縁膜と接す
る境界部分で絶縁膜の膜質が一様でないために絶縁性が
劣化する。十分な絶縁性を得るために、絶縁膜の膜厚を
厚くするには、熱酸化前の下層導電層の膜厚も厚くする
必要があり平坦性が悪くなる。また、形成され、る絶縁
膜表面は、熱酸化前の下層の導電層表面にくらべて凹凸
が増したものとなシ、後工程での加工を難しくする点が
ある。
Although the conventional method for forming an insulating film described above requires a small number of steps, it is very difficult to obtain an insulating film with a uniform thickness. The thickness of the insulating film becomes thinner on the sidewalls of the area, and the quality of the insulating film is not uniform at the boundary portion where it contacts the underlying insulating film, resulting in deterioration of insulation. In order to increase the thickness of the insulating film in order to obtain sufficient insulation, it is necessary to increase the thickness of the lower conductive layer before thermal oxidation, which deteriorates the flatness. Further, the surface of the insulating film formed has increased irregularities compared to the surface of the underlying conductive layer before thermal oxidation, which makes processing in subsequent steps difficult.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、絶縁膜を有する半導
体基板の一主面の所定領域に第1の導電膜とその上に第
1の酸化膜と酸化阻止膜が交互に積層する多層膜を形成
する工程と、全面に多結晶シリコン膜を形成する工程と
、前記多結晶シリコン膜を酸化性雰囲気中で全てシリコ
ン酸化膜に変換すると共に前記第1の導電膜と前記シリ
コン酸化膜の界面に第1の導電膜の酸化膜からなる第2
の酸化膜を形成する工程と、前記シリコン酸化膜を全て
エツチング除去する工程と、前記第2の酸化膜を介して
前記第1の導電膜と電気的に絶縁する第2の導電膜を形
成する工程を含むことを特徴とする。
The method for manufacturing a semiconductor device of the present invention includes forming a multilayer film in which a first conductive film and a first oxide film and an oxidation prevention film are alternately stacked on a predetermined region of one principal surface of a semiconductor substrate having an insulating film. forming a polycrystalline silicon film on the entire surface; and converting all of the polycrystalline silicon film into a silicon oxide film in an oxidizing atmosphere, and forming a polycrystalline silicon film on the interface between the first conductive film and the silicon oxide film. A second conductive film made of an oxide film of the first conductive film.
forming an oxide film, etching away all of the silicon oxide film, and forming a second conductive film electrically insulating from the first conductive film via the second oxide film. It is characterized by including a process.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(f)は本発明の一実施例の工程順縦断
面図である。シリコン酸化膜2を有するシリコン基板1
上に気相成長法によってポリシリコン膜3を堆積した後
、これにリン(P)等の不純物を含有せしめて良導電膜
とする。ポリシリコン膜3表面に熱酸化法によシシリコ
ン酸化膜4を形成し、さらにその上に気相成長法によシ
リコン9化膜5を形成する。ここで、シリコン酸化膜2
はシリコン基板1とポリシリコン膜3間を絶縁している
(第1図(a))。次に、シリコン窒化膜5とシリコン
酸化膜4及びポリシリコン膜3からなる3層膜の所望領
域以外の領域を写真食刻法によシエッチング除去しく第
1図(b) ) 、続いて全面にポリシリコン膜6を堆
積する(第1図(C))。次に、熱酸化法によりポリシ
リコン膜6を全てシリコン酸化膜7に変え、さらに熱酸
化を継続し、ポリシリコン膜3の側面を酸化する。ポリ
シリコン膜3は含有するリンによる増速効果のためシリ
コン基板1よシ速く酸化されるが、この酸化はポリシリ
コン膜3の側面に限られ、シリコン窒化膜5で酸化が阻
止された上面には及ばない(第1図(d))。次に、全
面を等方性のウェットエツチング液でエツチング除去し
てゆき、シリコン基板工に接するシリコン酸化膜2及び
7を全てエツチング除去し、ポリシリコン膜3の側面に
シリコン酸化膜7が残る状態で止める(第1図(e))
。最後に、露出したシリコン基板1表面に熱酸化法によ
シシリコン酸化膜8を所望の厚さに形成した後、上層の
導電層として、気相成長法でポリシリコン膜9を堆積し
、リンを含有せしめて良導電膜とし写真食刻法により所
望領域以外の領域をエツチング除去する(第1図(f)
)。
FIGS. 1(a) to 1(f) are longitudinal cross-sectional views in the order of steps of an embodiment of the present invention. Silicon substrate 1 having silicon oxide film 2
A polysilicon film 3 is deposited thereon by vapor phase growth, and then impurities such as phosphorus (P) are added to the polysilicon film 3 to make it a highly conductive film. A silicon oxide film 4 is formed on the surface of the polysilicon film 3 by a thermal oxidation method, and a silicon 9 oxide film 5 is further formed thereon by a vapor phase growth method. Here, silicon oxide film 2
provides insulation between the silicon substrate 1 and the polysilicon film 3 (FIG. 1(a)). Next, areas other than the desired areas of the three-layer film consisting of silicon nitride film 5, silicon oxide film 4, and polysilicon film 3 are removed by photoetching (Fig. 1(b)), and then the entire surface is etched. A polysilicon film 6 is deposited on the surface (FIG. 1(C)). Next, the entire polysilicon film 6 is changed into a silicon oxide film 7 by thermal oxidation, and the thermal oxidation is continued to oxidize the side surface of the polysilicon film 3. Polysilicon film 3 is oxidized faster than silicon substrate 1 due to the speed-enhancing effect of the phosphorus it contains, but this oxidation is limited to the side surfaces of polysilicon film 3, and oxidation is limited to the top surface where oxidation is prevented by silicon nitride film 5. (Fig. 1(d)). Next, the entire surface is etched away using an isotropic wet etching solution, and all of the silicon oxide films 2 and 7 in contact with the silicon substrate are etched away, leaving the silicon oxide film 7 on the side surface of the polysilicon film 3. (Fig. 1 (e))
. Finally, after forming a silicon oxide film 8 to a desired thickness on the exposed surface of the silicon substrate 1 by thermal oxidation, a polysilicon film 9 is deposited as an upper conductive layer by vapor phase epitaxy. The film is made into a highly conductive film, and the areas other than the desired areas are removed by photolithography (Fig. 1(f)).
).

本実施例によれば、ポリシリコン膜3の側面でシリコン
酸化膜7の膜厚が特に不均一な個所はなく、シリコン酸
化膜の膜質も一様であシ、かつポリシリコン膜3もさほ
ど酸化されないのでシリコン酸化膜7の膜厚を薄くする
ことができる。また、ポリシリコン膜6の熱酸化によシ
ボリシリコン膜3に鋭角の縁辺部や角部が残らないので
絶縁性は十分確保される。
According to this embodiment, there is no part where the thickness of the silicon oxide film 7 is particularly uneven on the side surface of the polysilicon film 3, the quality of the silicon oxide film is uniform, and the polysilicon film 3 is not oxidized much. Therefore, the thickness of the silicon oxide film 7 can be reduced. Furthermore, thermal oxidation of the polysilicon film 6 leaves no sharp edges or corners on the wrinkled silicon film 3, so that sufficient insulation is ensured.

第2図(a)〜(e)は、本発明の他の実施例の工程順
縦断面図である。シリコン酸化膜2上にシリコン窒化膜
10が積層された絶縁膜を有するシリコン基板1上に、
前記実施例と同様にしてポリシリコン膜3とシリコン酸
化膜4及びシリコン窒化膜5を形成し更に1 シリコン
窒化膜5の上に1シリコン酸化膜12とシリコン窒化膜
13を順次気相成長法によりて堆積し、この5層膜を所
定形状に加工する。この時、ポリクリコン膜3に対して
シリコン酸化膜及び窒化膜を選択的にエツチング除去す
る等方性のプラズマエツチングでまずシリコン窒化膜1
3、シリコン酸化膜12、シリコン窒化膜5及びシリコ
ン酸化膜4の6膜を順次エツチング除去した後、異方性
のプラズマエツチングでポリシリコン膜3をエツチング
除去する。次に、全面にポリシリコン膜6を堆積する(
第2図(a))。
FIGS. 2(a) to 2(e) are vertical cross-sectional views in the order of steps of another embodiment of the present invention. On a silicon substrate 1 having an insulating film in which a silicon nitride film 10 is laminated on a silicon oxide film 2,
A polysilicon film 3, a silicon oxide film 4, and a silicon nitride film 5 are formed in the same manner as in the previous embodiment, and then a silicon oxide film 12 and a silicon nitride film 13 are sequentially formed on the silicon nitride film 5 by vapor phase growth. This five-layer film is then processed into a predetermined shape. At this time, the silicon nitride film 1 is first etched by isotropic plasma etching that selectively etches the silicon oxide film and nitride film with respect to the polycone film 3.
3. After the six films of silicon oxide film 12, silicon nitride film 5, and silicon oxide film 4 are removed by etching in sequence, polysilicon film 3 is etched away by anisotropic plasma etching. Next, a polysilicon film 6 is deposited on the entire surface (
Figure 2(a)).

次にポリシリコン膜6を熱酸化し全てシリコン酸化膜7
に変え(第2図世))、続いて、シリコン窒化膜10上
及びシリコン窒化膜13上のシリコン酸化膜7を等方性
のウェットエツチングで除去し、ポリシリコン膜3の側
面にのみシリコン酸化膜7を残す(第2図(C))。次
に、表面に露出しているシリコン9化膜10及び13と
その直下にあるシリコン酸化膜2及び12を順次エツチ
ング除去し(第2図(d) ) 、次いで熱酸化法によ
シリコン基板表面にシリコン酸化膜8を形成した後、所
定形状のポリシリコン膜9を形成する(第2図(e))
Next, the polysilicon film 6 is thermally oxidized to form a silicon oxide film 7.
(Fig. 2)), and then the silicon oxide film 7 on the silicon nitride film 10 and the silicon nitride film 13 is removed by isotropic wet etching, and silicon oxide is formed only on the sides of the polysilicon film 3. The film 7 is left (FIG. 2(C)). Next, the silicon 9 oxide films 10 and 13 exposed on the surface and the silicon oxide films 2 and 12 immediately below them are sequentially etched away (FIG. 2(d)), and then the silicon substrate surface is removed by thermal oxidation. After forming a silicon oxide film 8, a polysilicon film 9 of a predetermined shape is formed (FIG. 2(e)).
.

本実施列では、シリコン基板表面はシリコン窒化膜10
で覆われているので前記実施例と異なシ酸化されない。
In this example, the silicon substrate surface is covered with a silicon nitride film 10.
Since it is covered with oxide, it is not oxidized unlike the previous embodiment.

また、シリコン窒化[10をエツチング除去する際、ポ
リシリコン膜3の上面はシリコン窒化膜が2層あるので
、エツチング時のオーバエツチングによってポリシリコ
ン膜上面の絶縁膜が過度に除去されてしまうことが防げ
る利点がある。
Furthermore, when removing silicon nitride [10] by etching, since there are two layers of silicon nitride films on the top surface of the polysilicon film 3, the insulating film on the top surface of the polysilicon film may be excessively removed due to overetching during etching. There are advantages to preventing this.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、下層導電膜パターン側面
に接し基板全面を覆うポリシリコン膜を全てシリコン酸
化膜に変え、さらに下層導電膜パターン側面とシリコン
酸化膜の接触する界面に下層導電膜の酸化膜を形成し、
前記シリコン酸化膜は全て除去し下層導電膜の酸化膜を
介して下層導電膜と電気的に絶縁した上層導電膜を形成
する。
As explained above, the present invention replaces the polysilicon film that is in contact with the side surface of the lower conductive film pattern and covers the entire surface of the substrate with a silicon oxide film, and furthermore, the lower conductive film is added to the interface where the side surface of the lower conductive film pattern and the silicon oxide film contact. Forms an oxide film,
The silicon oxide film is completely removed, and an upper conductive film is formed which is electrically insulated from the lower conductive film via the oxide film of the lower conductive film.

これKよシ、絶縁性に優れ、素子の平坦化及び微細化に
適した絶縁膜を形成することができる。
This makes it possible to form an insulating film that has superior insulating properties and is suitable for planarization and miniaturization of elements.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(f)は本発明の一実施例の工程順縦断
面図、第2図(a)〜(e)は本発明の他の実施例の工
程順縦断面図である。 1・・・・・・シリコン基板、2,4,7,8,11.
12・・・・・・シリコン酸化膜、3,6,9・・・・
・・ポリシリコン膜、5.10.13・・・・・・シリ
コン窒化膜。 代理人 弁理士  内 原   晋 7″゛コ・−一。
FIGS. 1(a) to (f) are vertical sectional views in the order of steps of one embodiment of the present invention, and FIGS. 2(a) to (e) are longitudinal sectional views in the order of steps of another embodiment of the present invention. . 1...Silicon substrate, 2, 4, 7, 8, 11.
12... Silicon oxide film, 3, 6, 9...
...Polysilicon film, 5.10.13...Silicon nitride film. Agent: Susumu Uchihara, Patent Attorney 7″゛ko・−1.

Claims (1)

【特許請求の範囲】[Claims] 絶縁膜を有する半導体基板の一主面の所定領域に第1の
導電膜とその上に第1の酸化膜と酸化阻止膜が交互に積
層する多層膜を形成する工程と、全面に多結晶シリコン
膜を形成する工程と、前記多結晶シリコン膜を酸化性雰
囲気中で全てシリコン酸化膜に変換すると共に前記第1
の導電膜と前記シリコン酸化膜の界面に第1の導電膜の
酸化膜からなる第2の酸化膜を形成する工程と、前記シ
リコン酸化膜を全てエッチング除去する工程と、前記第
2の酸化膜を介して前記第1の導電膜と電気的に絶縁す
る第2の導電膜を形成する工程を含むことを特徴とする
半導体装置の製造方法。
A step of forming a multilayer film in which a first conductive film and a first oxide film and an oxidation prevention film are alternately stacked on a predetermined region of one main surface of a semiconductor substrate having an insulating film, and polycrystalline silicon is formed on the entire surface. a step of forming a film, converting the polycrystalline silicon film into a silicon oxide film in an oxidizing atmosphere, and converting the polycrystalline silicon film into a silicon oxide film in the first
forming a second oxide film made of an oxide film of the first conductive film at the interface between the conductive film and the silicon oxide film; etching away the silicon oxide film entirely; and removing the second oxide film. A method for manufacturing a semiconductor device, comprising the step of forming a second conductive film that is electrically insulated from the first conductive film through the step of forming a second conductive film.
JP60218362A 1985-09-30 1985-09-30 Method for manufacturing semiconductor device Expired - Lifetime JPH0799745B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60218362A JPH0799745B2 (en) 1985-09-30 1985-09-30 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60218362A JPH0799745B2 (en) 1985-09-30 1985-09-30 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6278852A true JPS6278852A (en) 1987-04-11
JPH0799745B2 JPH0799745B2 (en) 1995-10-25

Family

ID=16718695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60218362A Expired - Lifetime JPH0799745B2 (en) 1985-09-30 1985-09-30 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0799745B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020113390A (en) * 2019-01-09 2020-07-27 株式会社東海理化電機製作所 Method for manufacturing organic el element, and organic el device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694767A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Semiconductor device
JPS57211251A (en) * 1981-06-23 1982-12-25 Toshiba Corp Manufacture of semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694767A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Semiconductor device
JPS57211251A (en) * 1981-06-23 1982-12-25 Toshiba Corp Manufacture of semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020113390A (en) * 2019-01-09 2020-07-27 株式会社東海理化電機製作所 Method for manufacturing organic el element, and organic el device

Also Published As

Publication number Publication date
JPH0799745B2 (en) 1995-10-25

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