JPS6340341A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS6340341A
JPS6340341A JP18383086A JP18383086A JPS6340341A JP S6340341 A JPS6340341 A JP S6340341A JP 18383086 A JP18383086 A JP 18383086A JP 18383086 A JP18383086 A JP 18383086A JP S6340341 A JPS6340341 A JP S6340341A
Authority
JP
Japan
Prior art keywords
film
insulating film
silicon oxide
conductive layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18383086A
Other languages
Japanese (ja)
Inventor
Hiroshi Takagi
洋 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18383086A priority Critical patent/JPS6340341A/en
Publication of JPS6340341A publication Critical patent/JPS6340341A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To operate the title semiconductor device at a high speed by reducing the capacitance between wirings by a method wherein the prescribed etching is performed respectively on the first and the second insulating films and the second and the third insulating films which can be etched mutually selectively. CONSTITUTION:An SiO2 film 2 is formed on a substrate 1, and a polycrystalline Si film 3A is formed thereon. An SiO2 film 6 is formed on the film 3A. Then, the film 6 is selectively removed, the film 3A is processed into a polycrystalline Si gate film 3 using the film 6 as a mask, and a pattern is formed by selectively removing the film 2 in the same manner as above. Then, an SiO2 4 is formed by thermally oxidizing the substrate 1, and a silicon nitride film 7 and an SiO2 8 are formed on the film 4. Subsequently, the film 8 is removed by performing an anisotropic etching. As a result, the film 8 is left on the sidewall part only of the film 3 in a self-alignment manner. Then, the films 4 and 7 are removed. Subsequently, a damageless SiO2 film 9 is formed by thermally oxidizing the substrate 1. Then, a polycrystalline Si gate film 5 is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法に関し、特に多層配線
間の層間絶縁膜の形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an interlayer insulating film between multilayer interconnections.

〔従来の技術〕[Conventional technology]

第2図は従来のこの種の技術を示す工程断面図である。 FIG. 2 is a process sectional view showing a conventional technique of this type.

第2図において、1はシリコン基板、2は第1層シリコ
ン酸化膜、3は第1層多結晶シリコンゲート膜、4Aは
シリコン基板上の第2層シリコン酸化膜、4Bは熱酸化
によシ第2層シリコン酸化膜4Aと同時に形成された第
1層多結晶シリコンゲート膜3上の層間絶縁膜としての
シリコン酸化膜、5は第2層多結晶シリコンゲート膜で
ある。さらにt□z1は第2層シリコン酸化膜4人の膜
厚で、tox2は層間絶縁膜4Bの膜厚である。
In FIG. 2, 1 is a silicon substrate, 2 is a first-layer silicon oxide film, 3 is a first-layer polycrystalline silicon gate film, 4A is a second-layer silicon oxide film on a silicon substrate, and 4B is a silicon oxide film formed by thermal oxidation. A silicon oxide film 5 is a second layer polycrystalline silicon gate film as an interlayer insulating film on the first layer polycrystalline silicon gate film 3 formed at the same time as the second layer silicon oxide film 4A. Further, t□z1 is the thickness of the second silicon oxide film, and tox2 is the thickness of the interlayer insulating film 4B.

またs  1ox3は第1層多結晶シリコンゲート膜3
の側壁に形成されたシリコン酸化膜の膜厚である。
Also, s1ox3 is the first layer polycrystalline silicon gate film 3
This is the thickness of the silicon oxide film formed on the sidewalls of .

次にこのような構造の形成方法について説明する@まず
、シリコン基板1上に第1層シリコン酸化膜2を全面に
形成し、次いでCVD法によって、第1層多結晶シリコ
ンゲート膜3となる多結晶シリコン膜を同じく全面に形
成する。その後、写真製版技術とエツチング技術を使っ
て、前記多結晶シリコン膜を所望のパターンに選択エツ
チングし、第1層多結晶シリコンゲート膜3とする。引
き続いて、この第1層シリコンゲート膜3をマスクとし
て、露出した前記第1層シリコン酸化膜2を除去する(
第2図(a))。なお、第1層シリコン酸化膜2の代シ
に、シリコン窒化膜またはシリコン酸化膜とシリコン窒
化膜との多層構造膜を用いても良い。
Next, a method for forming such a structure will be explained.@First, a first layer silicon oxide film 2 is formed on the entire surface of a silicon substrate 1, and then a polycrystalline silicon oxide film 2, which will become a first layer polycrystalline silicon gate film 3, is formed by CVD. A crystalline silicon film is also formed over the entire surface. Thereafter, using photolithography and etching techniques, the polycrystalline silicon film is selectively etched into a desired pattern to form a first layer polycrystalline silicon gate film 3. Subsequently, using this first layer silicon gate film 3 as a mask, the exposed first layer silicon oxide film 2 is removed (
Figure 2(a)). Note that instead of the first layer silicon oxide film 2, a silicon nitride film or a multilayer structure film of a silicon oxide film and a silicon nitride film may be used.

引き続いて、ウェハ全体を酸化雰囲気中で熱処理し、前
記シリコン基板1上に熱酸化膜である第2層シリコン酸
化膜4Aを形成する。この時、同時に前記第1層多結晶
シリコンゲート膜3も酸化され、その上壁および側壁に
シリコン酸化膜4Bが形成される(第2図(ロ))。こ
の後、第2層目の配線材料となる多結晶シリコン膜をC
VDで形成して、第2層多結晶シリコンゲート膜5とす
る(第2図(C))。
Subsequently, the entire wafer is heat-treated in an oxidizing atmosphere to form a second layer silicon oxide film 4A, which is a thermally oxidized film, on the silicon substrate 1. At this time, the first polycrystalline silicon gate film 3 is also oxidized, and a silicon oxide film 4B is formed on its upper and side walls (FIG. 2(b)). After this, the polycrystalline silicon film that will become the second layer wiring material is
It is formed by VD to form the second layer polycrystalline silicon gate film 5 (FIG. 2(C)).

以上のように、従来の半導体装置では、シリコン基板1
上の第2層シリコン酸化膜4人と第1層多結晶シリコン
ゲート膜3上のシリコン酸化膜4Bとが、酸化によシ同
時に形成されるために、いかなる酸化法を用いても、ま
た、第1層多結晶シリコンゲート膜3として不純物をド
ープした多結晶シリコンを使用しても、第2図(ロ)に
示したシリコン基板1上の酸化膜厚tOXlと第1層多
結晶シリコンゲート膜3の上面および側壁に形成された
酸化膜厚toxz * tOX3との関係は下記のよう
になる。
As described above, in the conventional semiconductor device, the silicon substrate 1
Since the four upper second layer silicon oxide films and the silicon oxide film 4B on the first layer polycrystalline silicon gate film 3 are formed simultaneously by oxidation, no matter what oxidation method is used, Even if polycrystalline silicon doped with impurities is used as the first layer polycrystalline silicon gate film 3, the oxide film thickness tOXl on the silicon substrate 1 shown in FIG. The relationship between the thickness of the oxide film toxz*tOX3 formed on the top surface and sidewalls of 3 is as follows.

2 toxl (toxz≦5tox1  ・・・・・
・ (1)2 taxi (tOx3≦3tox1  
・・・・・・ (2)〔発明が解決しようとする問題点
〕 一般に、半導体装置においては、各層の配線の信号伝達
速度を高めるために、配線間の容量を可能な限シ低減し
たい。そのためには、第2図0)における第1層多結晶
シリコンゲート膜3の上面のシリコン酸化膜厚tox2
および側面のシリコン酸化膜厚tox3はできるだけ大
きくしたい。他方、半導体装置の集積度が向上するに従
って、トランジスター等を構成するシリコン基板1上の
シリコン酸化膜4Aの膜厚t OXIは必然的に小さく
ならざるを得ない。ところが、上述したように従来の方
法をとる限シ、両者の間には(1) 、 (21式の関
係が成立するため、toxlを小さくすると、tox2
およびtox3も同様に小さくなシ、配線間の容量が増
大する結果となる。
2 toxl (toxz≦5tox1...
・ (1) 2 taxi (tOx3≦3tox1
(2) [Problems to be Solved by the Invention] Generally, in a semiconductor device, in order to increase the signal transmission speed of the wiring in each layer, it is desired to reduce the capacitance between the wiring as much as possible. For this purpose, the silicon oxide film thickness tox2 on the upper surface of the first layer polycrystalline silicon gate film 3 in FIG.
It is desired that the silicon oxide film thickness tox3 on the sides and sides be as large as possible. On the other hand, as the degree of integration of semiconductor devices increases, the thickness tOXI of the silicon oxide film 4A on the silicon substrate 1 forming transistors and the like inevitably becomes smaller. However, as mentioned above, as long as the conventional method is used, the relationship (1) and (21) hold between the two, so if toxl is decreased, tox2
Similarly, tox3 is also small, resulting in an increase in the capacitance between the wirings.

この発明は、上記のような問題点を解決するためになさ
れたもので、配線間容量が低く、高速動作が可能で、し
かも集積度の高い半導体装置な得ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor device having low inter-wiring capacitance, capable of high-speed operation, and having a high degree of integration.

〔問題点を解決する九めの手段〕[Ninth way to solve the problem]

この発明に係る半導体装置の製造方法は、第1層導電層
を覆う第1の絶縁膜を形成した後、とれらを覆って、第
2および第3の絶縁膜を形成する。
In the method for manufacturing a semiconductor device according to the present invention, a first insulating film covering a first conductive layer is formed, and then second and third insulating films are formed to cover them.

このとき、第1と第2.第2と第3の絶I&膜は、相互
に選択的にエツチング可能外ものとする。次いで、第3
の絶縁膜に異方性エツチングを施し、第1層導電層の側
壁部のみ残してこれを除去する。
At this time, the first and second . The second and third isolation films are not capable of being selectively etched with respect to each other. Then the third
The insulating film is subjected to anisotropic etching to remove the first conductive layer, leaving only the side wall portion.

さらに第3の絶縁膜に覆われていない第2の絶縁膜をエ
ツチングにより除去し、第1層導電層を形成しない部分
に露出させた半導体基板表面に、第4の絶縁膜を形成す
る。
Further, the second insulating film that is not covered with the third insulating film is removed by etching, and a fourth insulating film is formed on the surface of the semiconductor substrate exposed in the portion where the first conductive layer is not formed.

〔作用〕[Effect]

第1層導電層上の第1の絶縁膜と、第1層導電層を形成
しない部分の半導体基板上の第4の絶縁膜とは、全く独
立に形成され、例えば第1の絶縁膜のみCVD法により
厚く形成することも自在でおる。また、異方性エツチン
グを利用して第1層導電層の側壁部に第3の絶縁膜を残
すどとによシ、この部分の層間絶縁膜の膜厚も大きくな
る。
The first insulating film on the first conductive layer and the fourth insulating film on the portion of the semiconductor substrate where the first conductive layer is not formed are formed completely independently, for example, only the first insulating film is formed by CVD. It is also possible to form it thickly by a method. Furthermore, if the third insulating film is left on the side wall portion of the first conductive layer using anisotropic etching, the thickness of the interlayer insulating film in this portion also increases.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図に右いて、シリコン基板1の上に当該シリコン基板1
を熱酸化して第1層シリコン酸化M2を形成し、その上
に第1層多結晶シリコン膜3人を形成する(第1図(a
))。
An embodiment of the present invention will be described below with reference to the drawings. 1st
On the right side of the figure, the silicon substrate 1 is placed on top of the silicon substrate 1.
A first layer of silicon oxide M2 is formed by thermal oxidation, and three first layer polycrystalline silicon films are formed thereon (see FIG. 1(a)).
)).

引き続いて第1層多結晶シリコン膜3A上に、CVD法
によってシリコン酸化膜6を形成する(第1図(b))
Subsequently, a silicon oxide film 6 is formed on the first layer polycrystalline silicon film 3A by the CVD method (FIG. 1(b)).
.

次に、写真製版技術とエツチング技術を利用して、シリ
コン酸化膜6を選択的に除去し、引続き当該シリコン酸
化H1X6をマスクとして第1層多結晶シリコン膜3人
を第1層多結晶シリコンゲート膜3に加工し、同様に第
1層シリコン酸化膜2を連続的に選択除去して、所望の
パターンを形成する(第1図(C))。
Next, using photolithography and etching techniques, the silicon oxide film 6 is selectively removed, and then, using the silicon oxide H1X6 as a mask, the three first layer polycrystalline silicon films are formed into a first layer polycrystalline silicon gate. Similarly, the first layer silicon oxide film 2 is successively and selectively removed to form a desired pattern (FIG. 1(C)).

次に、シリコン基板1を熱酸化して第2層シリコン酸化
膜4を形成し、さらにCVD法またはNs雰囲気中で熱
処理する方法により、前記第2層シリコン酸化膜4上全
面にシリコン窒化膜7を形成する(第1図(d))。
Next, the silicon substrate 1 is thermally oxidized to form a second layer silicon oxide film 4, and then a silicon nitride film 7 is formed over the entire surface of the second layer silicon oxide film 4 by a CVD method or a heat treatment method in an Ns atmosphere. (Fig. 1(d)).

さらに、CVD法を利用して、シリコン酸化膜8を形成
する(第1図(C))。その後、RIE (React
ive Ion Etching)法によって、上記シ
リコン酸化膜8を除去する。この時、シリコン窒化膜7
との界面でエツチングを停止する(第1図(f))。適
当なエツチング条件を選択することによって、シリコン
酸化wX8とシリコン窒化膜7とのエツチング選択比を
充分に大きくとることができ、容易にシリコン窒化膜7
との界面でエツチングを停止できる。異方性エツチング
でらるRIEを利用したことによシ、マスク等を用いる
ことなく、第1層多結晶シリコンゲート膜3の側壁部の
みに、シリコン酸化膜8を自己整合的に残すことができ
る。
Furthermore, a silicon oxide film 8 is formed using the CVD method (FIG. 1(C)). After that, RIE (React
The silicon oxide film 8 is removed by the ive ion etching method. At this time, silicon nitride film 7
Etching is stopped at the interface with (FIG. 1(f)). By selecting appropriate etching conditions, the etching selectivity between silicon oxide wX8 and silicon nitride film 7 can be made sufficiently large, and silicon nitride film 7 can be easily etched.
Etching can be stopped at the interface. By using RIE using anisotropic etching, the silicon oxide film 8 can be left in a self-aligned manner only on the sidewalls of the first layer polycrystalline silicon gate film 3 without using a mask or the like. can.

次に、シリコン窒化膜7をエツチング技術を用いて除去
しく第1図(2))、さらにシリコン基板1上の第2層
シリコン酸化膜4を除去する(第1図Φ))。その後、
改めてシリコン基板1を熱酸化してシリコン酸化膜9を
形成する。これは、このシリコン基板1上のシリコン酸
化膜の品質が、装置の特性に大きな影響を及ぼすことか
ら、それ以前のプロセスにおいてダメージを受けている
シリコン酸化膜4を除去し、ダメージのないシリコン酸
化膜9と交換したものである。次いで、CVD法を用い
て第2層多結晶シリコンゲート膜5を形成する(第1図
(i))。
Next, the silicon nitride film 7 is removed using an etching technique (FIG. 1 (2)), and the second layer silicon oxide film 4 on the silicon substrate 1 is also removed (FIG. 1 Φ)). after that,
The silicon substrate 1 is thermally oxidized again to form a silicon oxide film 9. This is because the quality of the silicon oxide film on the silicon substrate 1 has a great influence on the characteristics of the device, so the silicon oxide film 4 that has been damaged in the previous process is removed and the silicon oxide film is oxidized without damage. This was replaced with membrane 9. Next, a second layer polycrystalline silicon gate film 5 is formed using the CVD method (FIG. 1(i)).

以上説明した実施例に詔いて、第2層シリコン酸化膜4
の形成は、熱酸化法の代夛にCVD法等の堆積法を用い
て行なってもよい。
Based on the embodiment described above, the second layer silicon oxide film 4
may be formed using a deposition method such as a CVD method instead of a thermal oxidation method.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、異方性エツチングの
利用によシ余分なマスク等を用いる必要もなく、第1層
導電層の側壁部を含めて眉間絶縁膜を厚く形成できる一
方、第1層導電層のない半導体基板上の絶縁膜は、上記
層間絶縁膜とは独立に薄く形成できるため、配線間容量
が低く、高速動作が可能になるとともに1集積度の高い
半導体装置が得られる効果がある。
As described above, according to the present invention, it is possible to form a thick glabella insulating film including the side wall portion of the first conductive layer without using an extra mask by using anisotropic etching. Since the insulating film on the semiconductor substrate without the first conductive layer can be formed thinly independently of the interlayer insulating film, the inter-wiring capacitance is low, high-speed operation is possible, and a semiconductor device with a high degree of integration can be obtained. It has the effect of

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す工程断面図、第2図は
従来例を示す工程断面図である。 1・・・・シリコン基板、3・・争・第1層多結晶シリ
コンゲート膜、4,6,8,9・・・・シリコン酸化膜
、5・・・・・第2層多結晶シリコンケー)Jl、7・
m−・シリコン窒化膜。
FIG. 1 is a process sectional view showing an embodiment of the present invention, and FIG. 2 is a process sectional view showing a conventional example. 1... Silicon substrate, 3... First layer polycrystalline silicon gate film, 4, 6, 8, 9... Silicon oxide film, 5... Second layer polycrystalline silicon case. ) Jl, 7・
m-・Silicon nitride film.

Claims (4)

【特許請求の範囲】[Claims] (1)半導体基板表面上に選択的に第1層導電層を形成
する工程と、この第1層導電層を覆う第1の絶縁膜を形
成する工程と、これら第1層導電層および第1の絶縁膜
を覆つて、第1の絶縁膜に対して選択的にエッチング可
能な第2の絶縁膜および当該第2の絶縁膜に対して選択
的にエッチング可能な第3の絶縁膜を順次形成する工程
と、第3の絶縁膜に異方性エッチングを施し、第1層導
電層の側壁部のみ残して当該第3の絶縁膜を除去する工
程と、第3の絶縁膜に覆われていない第2の絶縁膜をエ
ッチングにより除去し、第1層導電層を形成しない部分
に半導体基板表面を露出させる工程と、露出した半導体
基板表面に第4の絶縁膜を形成する工程と、第2層導電
層を形成する工程とを含むことを特徴とする半導体装置
の製造方法。
(1) A step of selectively forming a first conductive layer on the surface of a semiconductor substrate, a step of forming a first insulating film covering this first conductive layer, and a step of forming a first conductive layer and a first conductive layer. A second insulating film that can be selectively etched with respect to the first insulating film and a third insulating film that can be selectively etched with respect to the second insulating film are sequentially formed to cover the insulating film. a step of performing anisotropic etching on the third insulating film and removing the third insulating film leaving only the side wall portion of the first conductive layer; a step of removing the second insulating film by etching and exposing the surface of the semiconductor substrate in a portion where the first conductive layer is not formed; a step of forming a fourth insulating film on the exposed surface of the semiconductor substrate; 1. A method of manufacturing a semiconductor device, comprising the step of forming a conductive layer.
(2)第1および第3の絶縁膜をシリコン酸化膜とし、
少なくとも第1層導電層上の第1の絶縁膜および第3の
絶縁膜をそれぞれCVD法により形成することを特徴と
する特許請求の範囲第1項記載の半導体装置の製造方法
(2) The first and third insulating films are silicon oxide films,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film and the third insulating film on at least the first conductive layer are each formed by a CVD method.
(3)第2の絶縁膜をシリコン窒化膜とし、CVD法に
より形成することを特徴とする特許請求の範囲第2項記
載の半導体装置の製造方法。
(3) The method of manufacturing a semiconductor device according to claim 2, wherein the second insulating film is a silicon nitride film and is formed by a CVD method.
(4)第2の絶縁膜をシリコン窒化膜とし、第1の絶縁
膜を構成するシリコン酸化膜を窒化処理することにより
形成することを特徴とする特許請求の範囲第2項記載の
半導体装置の製造方法。
(4) The semiconductor device according to claim 2, wherein the second insulating film is a silicon nitride film, and the silicon oxide film constituting the first insulating film is formed by nitriding. Production method.
JP18383086A 1986-08-04 1986-08-04 Manufacture of semiconductor device Pending JPS6340341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18383086A JPS6340341A (en) 1986-08-04 1986-08-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18383086A JPS6340341A (en) 1986-08-04 1986-08-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6340341A true JPS6340341A (en) 1988-02-20

Family

ID=16142590

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18383086A Pending JPS6340341A (en) 1986-08-04 1986-08-04 Manufacture of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007207784A (en) * 2006-01-30 2007-08-16 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007207784A (en) * 2006-01-30 2007-08-16 Toshiba Corp Semiconductor device

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