JPS6278637A - Memory system for working history - Google Patents

Abstract

PURPOSE:To attain the effective application of system resources by reading out plural trace memories all at once and for each clock. CONSTITUTION:An address signal generating circuit 3 supplies both a clock CLK and a read/write designating signal RW and produces an address signal ADD having a double cycle as much as the clock CLK as long as the signal RW designates a writing action. While the signal ADD having the same cycle as the CLK is produced when a reading action is designated. These two signals ADD are stored in an address register 5 and then supplied in common to trace memories 1 and 2. Therefore the working history data is written alternately to both memories 1 and 2 against the same signal ADD. Then the history data is read out simultaneously from both memories 1 and 2 in response to the signal ADD and sent to read registers 7 and 8 successively.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an operation history storage system, particularly an operation history storage system for an external memory bag m1 human output processing device (hereinafter referred to as the device) that operates in synchronization with a clock. The present invention relates to an operation history storage method in which data is read out via a bus used for normal operation data exchange with center system devices such as a central processing unit and a main storage device.

[Conventional technology]

- Generally speaking, in order to perform a sufficient analysis of equipment failures, it is important to know the point at which the failure occurred (・) and the lack of information. Wagyu j,
2 bu? 2. Information going back in time to a certain extent is required. For this reason, the device designer selects information that the device designer deems appropriate, such as commands and address signals for the device, and writes it to a dedicated memory (trace memory) in synchronization with the device operation. The writing is then stopped, the contents written in the trace memory are read out, and the read contents are used for failure analysis.

The conventional operation history storage method includes only one trace memory, and writes data from the device to be stored and reads the data to an external device such as a diagnostic processor in units of one address per clock.

[Problem that the invention seeks to solve]

In such a conventional operation history storage method, only the reading of the trace memory is performed by the central processing unit during normal operation.
This is done for each address via the bus used for exchanging data with center system devices such as the main storage device, so reading the trace memory may interfere with the above data exchange, reducing the throughput of the computer system. There is a point. For example, if a correctable error occurs in an external storage device, the external history device can still be used, so the trace memory must be read quickly, and the central processing unit must be able to access the failed device. When attempting to write, it is necessary to read the trace memory very quickly and quickly find out the details of the failure (availability, etc.) As the amount of data exchanged between devices increases and the speed of data exchange increases, the above-mentioned problems are becoming more and more multicultural, and the bit width of the operation history data stored in the trace memory is increasing. It is different from the bit width of data exchanged during normal operation.

[Means for solving problems]

The operation history storage method of the present invention is an operation history storage method in which operation history data of a device that operates in synchronization with a clock is read out via a bus used for data exchange during normal operation. It consists of a plurality of memories, each of which is commonly supplied with an address signal, write data, and a read signal, and each of which is individually supplied with a write signal, and which generates an address signal with a period equal to the clock times the number of memories during a write operation. During a read operation, during a write operation, a write signal generation circuit is provided that sequentially generates write signals for the number of memories whose phase is shifted by l clock between the same address signals, and a write signal generation circuit is provided to generate write signals for the number of memories whose phase is shifted by l clock between the same address signals, and to generate data to be stored in a predetermined operation history in the device. are sequentially written as write data in the memory in response to a write signal, and read out from all the memories to the bus at once in response to a read signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2(a) and (b) are operational waveform diagrams for explaining the operation of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. 1 is a system configuration diagram showing an example of a computer system to which the embodiment shown in FIG.

First, an example of a computer system to which the embodiment shown in FIG. 1 is applied will be explained with reference to FIG. 3.The computer system shown in FIG.
0. Main storage device 200, diagnostic processor 300, communication processor 400. I/O processor 500. A mass storage processor 600 and an external storage device 700 are connected to a bus 800.
Data is processed while exchanging data with each other via 00.

The diagnostic processor 300, which together with the central processing unit 100 and the main storage device 200 constitutes a center system device, does not operate during normal operation, and the central processing unit 100. Main storage device 2
002 communication processor 400. Input/output processor 500
．． It is activated when a failure occurs in either the mass storage processor 600 or the external storage device 700.

Communication processor 400. Input/output processor 500° mass storage processor 600 and external storage device 700
(hereinafter referred to as the device) is provided with an operation history storage means as shown in Figure 1 as necessary, and information that the device designer deems appropriate, such as commands and addresses within the device during normal operation, is selected. The data is written sequentially, and when a failure occurs, the written contents are read out to the diagnostic processor 300 via the bus 800 and used for failure analysis. Such operation history data for failure analysis is stored on the bus 800 during normal operation.
For example, if the data flowing above is 64 bits, at most 3
It is about 2 bits.

Next, the operation will be explained with reference to FIG. 1 showing one embodiment of the present invention.

The operation history storage system shown in FIG. 1 includes two trace memories 1 and 2, an address signal generation circuit 3, a write signal generation circuit 4, an address register 5, a trace data register 6, and two read data registers 7. and 8
, a multiplexer 9, and two AND gates 10 and 11.

A clock CLK and a read/write designation signal RW supplied from the core of the 3-piece address signal generation circuit are input, and if the read/write designation signal RW designates a write operation, the clock CLK is input.
It generates an address signal ADD with a cycle twice that of the clock CLK, and in the case of designating a read operation, generates an address signal ADD with the same cycle as the clock CLK, holds each in the address register 5, and stores them in the trace memory. 1 and 2 in common.

The write signal generation circuit 4 inputs the clock CLK and the read/write designation signal RW, and in the case of write operation designation, the write signal WEI for the trace memory 1 and the write signal W for the trace memory 2 are generated during the same address signal ADD.
E2 is generated sequentially for each clock CLK.

The AND gate 10 performs a logical product of the write signal WEI and the write pulse WP from the core of the device and supplies the write pulse WP+ to the trace memory 1.
takes the AND of the write signal WE2 and the write pulse WP and supplies the write pulse WP2 to the trace memory 2.

The trace data register 6 holds operation history data DDA from the core of the device and supplies it to the trace memories 1 and 2 in common. Further, the read data registers 7 and 8 hold each read data from the trace memories 1 and 2, respectively, and supply it to the multiplexer 9, and the multiplexer 9 receives the normal data from the device core when there is no error signal ER from the device core. Accepts operation data NDA, and when error signal ER is present, read data registers RD1 and R
It receives the output from D2 and outputs each to bus 800.

Now, when the read/write designation signal RW designates a write operation, the important signals are as shown in FIG. Second. Fifth... operation history data DDl, DD3. DD5... are address signals ADl, AD2 . AD3...
The second . 4th. 6th...
Operation history data of DD2, DD4, DD6・
...is the address number ADI, AD2, AD
Write pulse WP2 to the address specified by 3.
written in response to. That is, the address signal ADI
, AD2°AD3... are generated every two clock CLKs, and in response to write pulses WPI and WF2 that occur every two clock CLKs between each,
Two trace memories 1 and 2 for the same address signal
Writing is performed alternately.

When writing such operation history data, an error signal ER is generated.
continues as long as no error occurs and the device is operating normally,
During this time, the multiplexer 9 accepts the normal operation data NDA as described above and outputs it to the bus 800, and the central processing unit 100. The data is supplied to the main storage device 200 or other devices.

io- Next, when a failure occurs in the device, the read/write designation signal RW switches to read operation designation, and the error signal ER
is input, so each output of the nine read data registers 7 and 8 is received by the multiplexer.

During a read operation, as shown in FIG. 2(b), address signals ADI, AD2, AD3... are generated every clock CLK, and data is read from trace memories 1 and 2 in response to these address signals. Read data D11 at the same time
and D21. D12 and D22. D13 and D23...
. . are sequentially read out into the read data registers 7 and 8, respectively, and supplied to the diagnostic processor 3 via the bus 800. The total bit width of read data RDt and RD2 is comparable to that of normal operation data NDA.

In the embodiment described above, two sets of trace memories are provided, but the present invention is not limited to this, and three or more sets may be provided.

When N types of trace memories are provided, the address signal generation circuit generates an address signal whose period is N times the clock period during a write operation, and the write signal generation circuit generates an address signal whose period is N times the clock period during a write operation. ．． Of course, N write signals whose phases are shifted by each clock are generated and sequentially supplied to each trace memory.

[Effects of the Invention] The operation history storage method of the present invention can read out a plurality of trace memories at once for each clock, so reading out operation history data is easier than sending and receiving normal operation data via a bus. The effect is that system resources can be used more effectively because the degree of interference is reduced, contributing to improved computer system throughput, and the bit widths on the buses for operation history data and normal operation data can be made approximately equal. There is.

[Brief explanation of drawings]

Figure 1 is a block diagram showing one embodiment of the present invention, Figure 2 (
a) (Operation waveform diagram for explaining the operation of this embodiment shown in the blit 1st diagram, FIG. 3 is a system configuration diagram showing an example of a computer system to which the embodiment shown in FIG. 1 is applied. 1.2...Trace memory, 3...Address signal generation circuit, 4...Write signal generation circuit, 5...Address register, 6...・・・・・・
Trace data register, 7, 8... Read data register, 9... Multiplexer, 10.
11...AND gate, 100...- Central processing unit, 200... Main memory device, 300...
...Diagnostic processor, 400 ... Communication processor, 500 ... Input/output processor, 60
0...Mass storage processor, 700...
...external storage device, 800 ... bus.

Claims (1)

[Claims] An operation history storage method in which operation history data of a device that operates in synchronization with a clock is read out via a bus used for data exchange during normal operation; a plurality of memories, each of which is commonly supplied with an address signal, write data, and read signal, and each of which is individually supplied with a write signal; an address signal generation circuit that generates the address signal having the same period as the clock during a read operation, and a write signal for the number of memories whose phase is shifted by one clock between the same address signal during the write operation; a write signal generation circuit that sequentially generates a write signal, and sequentially writes predetermined operation history storage target data in the device as the write data into the memory in response to the write signal, and in response to the read signal. An operation history storage method characterized in that all the memories are read out to the bus at once.