JPS6277715A - Waveform shaping circuit - Google Patents
Waveform shaping circuitInfo
- Publication number
- JPS6277715A JPS6277715A JP21830585A JP21830585A JPS6277715A JP S6277715 A JPS6277715 A JP S6277715A JP 21830585 A JP21830585 A JP 21830585A JP 21830585 A JP21830585 A JP 21830585A JP S6277715 A JPS6277715 A JP S6277715A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- level
- waveform
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明はデジタルデータ伝送回路の波形整形回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a waveform shaping circuit for a digital data transmission circuit.
(従来の技術とその問題点)
従来このような波形整形回路の多くは、信号のピーク値
をホールドし、このホールド値の%のレベルを基準にし
てコンパレータに加え、このレベル以上では1、未満で
は0と判定させる。(Prior art and its problems) Conventionally, many of these waveform shaping circuits hold the peak value of a signal, add it to a comparator based on a level of % of this hold value, and when the level is above this level, it is 1, and less than 1. Then let it be determined as 0.
このような従来のピーク値ホールド方式の回路例として
は、たとえば第4図に示すようなものが知られている。As an example of such a conventional peak value hold type circuit, for example, the one shown in FIG. 4 is known.
この場合、入力端子31からの信号の一方はコンパレー
タ38の子端子に直接入力し、分岐点40からの分岐信
号はコンデンサ34によってピークホールドされる。ホ
ールドされたピーク値は利得1のバッファ35を介し、
ボリウム36によって2レベルとしてコンパレータ38
の一端子に入力させて基準値とし、前記直接の入力信号
と比較して出力端子39に出力させる。In this case, one of the signals from the input terminal 31 is directly input to the child terminal of the comparator 38 , and the branch signal from the branch point 40 is peak-held by the capacitor 34 . The held peak value is passed through a buffer 35 with a gain of 1,
Comparator 38 as two levels by volume 36
The reference value is inputted to one terminal of , and is compared with the direct input signal and outputted to the output terminal 39 .
この方法の欠点は、ピークホールドの時定数の決定が困
難である。即ちこのような回路では、コンデンサ34.
抵抗33によるピークホールドの特定数の設定を入力信
号に適正に対応した値にするのが困難で、実際上正確に
信号伝達が行われ轢くなり、時定数が長ずぎると信号レ
ベルの急変に追従出来ず、短すぎるとピーク、ボトムの
中間値としての基準レベルの役割が失われる。A disadvantage of this method is that it is difficult to determine the peak hold time constant. That is, in such a circuit, capacitor 34.
It is difficult to set the specific number of peak holds by the resistor 33 to a value that properly corresponds to the input signal, and in reality, the signal transmission is not carried out accurately, and if the time constant is too long, it will not follow sudden changes in the signal level. If it is not possible and it is too short, the role of the reference level as an intermediate value between the peak and the bottom will be lost.
(問題を解決するための手段)
本発明は上述のような問題を解決し、ピークホールドせ
ずに波形整形を行う回路を提供することを目的とする。(Means for Solving the Problems) An object of the present invention is to solve the above problems and provide a circuit that performs waveform shaping without peak holding.
即ち、入力信号を遅延させる遅延回路を設け、この遅延
回路の出力を前記コンパレータの比較基準として用いる
ものである。That is, a delay circuit is provided to delay an input signal, and the output of this delay circuit is used as a comparison reference for the comparator.
さらに波形により前記遅延回路の出力を結果的に圧縮す
る固定レベル付与回路も設け、この固定レベル付与回路
の出力を前記コンパレータの比較基準として用いるもの
である。Furthermore, a fixed level applying circuit is also provided which compresses the output of the delay circuit according to the waveform, and the output of this fixed level applying circuit is used as a comparison standard for the comparator.
(作用)
」二連のように設定困難なピークホールド値を用いずに
、入力信号を遅延させ、もしくは更に圧縮して比較箪準
信号として用いるので、この基準信号レベルに対し入力
信号レベルが増大の時はON、減少の時はOFFとなる
ようにすることにより、相当に歪んだ入力信号にだいし
ても確実に入力信号に対応した矩形波を得ることが出来
る。(Function) Since the input signal is delayed or further compressed and used as a comparison signal without using a peak hold value that is difficult to set as in the case of two series, the input signal level increases with respect to this reference signal level. By turning on when the signal is on and turning off when the signal is decreasing, it is possible to reliably obtain a rectangular wave corresponding to the input signal even if the input signal is considerably distorted.
(実施例) 第1図は本発明の実施例の回v8構成図である。(Example) FIG. 1 is a block diagram of a circuit v8 according to an embodiment of the present invention.
入力端子1から入った信号を分岐点10で分岐し、抵抗
2,3で構成された分圧回路11でピーク値を分割、レ
ベルダウンし、抵抗2及び3とmlンデンサ4で構成さ
、れた遅延回路12で遅延する。この信号を利得1のバ
ッファ5を経由してボトム側の固定レベルを固定レベル
付与回路にで付与し、コンパレータ8へ比較基準レベル
として供給L7、出力端子9に波形整形された出力波形
として出力する。The signal input from input terminal 1 is branched at branch point 10, the peak value is divided and leveled down by voltage divider circuit 11 composed of resistors 2 and 3, and voltage divider circuit 11 composed of resistors 2 and 3 and ml capacitor 4 is used. The signal is delayed by a delay circuit 12. This signal is passed through a buffer 5 with a gain of 1, a fixed level on the bottom side is given to a fixed level giving circuit, and is supplied to a comparator 8 as a comparison reference level L7, and is outputted as a waveform-shaped output waveform to an output terminal 9. .
かかる如き本発明の回路構成によれば、ご1ンパレータ
8に入る信号の一部を分岐して、これをC3Rで構成し
た遅延回路12に入力し、該遅延回1t’812の出力
を基準レベルとするので、基準レベルに対し信号レベル
が増大した時点でONとなって出力波形が立上がり、逆
に減少した時点でOFFとなって出力波形は立下がる。According to the circuit configuration of the present invention, a part of the signal entering the first comparator 8 is branched and inputted to the delay circuit 12 composed of C3R, and the output of the delay circuit 1t'812 is set to the reference level. Therefore, when the signal level increases with respect to the reference level, it turns on and the output waveform rises, and when it decreases, it turns off and the output waveform falls.
本発明の特徴的な構成はこの部分にあり、実際にはピー
クレベルの平坦部(飽和状態)とボトムレベルの平坦部
(基準状!f3)が存在する場合があるが、この場合1
コはピーク側は基準レベルを抵抗比でレベルダウンする
か、又は遅延回路のロスでレベルダウンする。又ボトム
側は0レベルよりやや高いレベルを基準状態とした固定
レベルを付加することにより、どんな入力波形に対して
も波形整形が可能となる。The characteristic structure of the present invention is in this part.Actually, there may be a flat part of the peak level (saturated state) and a flat part of the bottom level (standard state! f3), but in this case, 1
On the peak side, the reference level is lowered by the resistance ratio, or by loss in the delay circuit. Furthermore, by adding a fixed level to the bottom side with the reference state being a level slightly higher than the 0 level, it becomes possible to shape the waveform of any input waveform.
第2図は上記回路の各部の動作を示す信号波形の関係を
示す。第1図の入力端子1 ((a1点〕の入力信号
21〔第2図(a)〕は分圧回路11と遅延回路12を
介して第1図(bl点に遅延信号波形22〔第2図(b
)〕を生ずる。この波形22のピーク値は抵抗2.3で
構成されている分圧回路1】でレベルダウンされて、第
2図(blに示すように入力信号波形21(破線)のピ
ーク値よりやや低い値に設定される。この遅延信号はバ
ッファ5を介して固定レベル付与回路6により、第2図
(C)に示すように入力信号波形21(破線)00レベ
ルよりもやや高い基準状態の固定レベルにボトム側が設
定され、結果的に入力信号が圧縮された形感の比較基準
信号波形23(第1図(C1点〕として、コンパレータ
8に与えられる。FIG. 2 shows the relationship of signal waveforms indicating the operation of each part of the circuit. The input signal 21 [FIG. 2 (a)] of the input terminal 1 ((point a1) in FIG. Figure (b
)]. The peak value of this waveform 22 is leveled down by the voltage divider circuit 1 consisting of resistors 2.3, and is slightly lower than the peak value of the input signal waveform 21 (dashed line) as shown in FIG. This delayed signal is set to a fixed level of a reference state slightly higher than the input signal waveform 21 (broken line) 00 level as shown in FIG. The bottom side is set, and as a result, the input signal is given to the comparator 8 as a comparison reference signal waveform 23 (FIG. 1 (point C1)) with a compressed feel.
従って出力端子9〔第1図id1点〕には、入力信号波
形21が比較基準信号波形23に対し下方から交叉した
時点で立ち上がり、同様に−1一方から交叉した時点で
立ち下がる矩形波24〔第2図(d)〕が出力される。Therefore, at the output terminal 9 [point ID1 in Figure 1], there is a rectangular wave 24 [that rises when the input signal waveform 21 crosses the comparison reference signal waveform 23 from below, and similarly falls when it crosses -1 from the other side]. FIG. 2(d)] is output.
なお本発明によれば入力信号として正弦波、三角波等の
飽和値のない波形の場合の整形においては、前記の圧縮
操作は必ずしも必要ではない。第3図は上述の状態を示
したもので、正弦波の場合を示している。According to the present invention, the above-described compression operation is not necessarily necessary when shaping an input signal having a waveform without a saturation value, such as a sine wave or a triangular wave. FIG. 3 shows the above-mentioned state, and shows the case of a sine wave.
(発明の効果)
上述のようにデジタル化した矩形波が三角波又は正弦波
の様に変形してしまっていても、その変化を捉えて安定
して、確実に再整形することが出来る。また部分的に波
形のなまっているものも、増加傾向になまった部分はO
N、減少傾向になまった部分はOFFとなるため、いか
なる場合でも波形整形が容易に出来る。(Effects of the Invention) As described above, even if the digitalized rectangular wave is deformed into a triangular wave or a sine wave, the change can be captured and reshaped stably and reliably. In addition, even if the waveform is partially distorted, the part where the increasing trend has become dull is O
N. Since the portion where the decreasing trend has stopped is turned off, waveform shaping can be easily performed in any case.
第1図は本発明の実施例の回路構成図、第2図は各部の
信号波形図、第3図は本発明の場合の正弦波の時の信号
波形図、第4図は従来の回路構成図である。
6:固定レベル付与回路、8:コンパレータ。Fig. 1 is a circuit configuration diagram of an embodiment of the present invention, Fig. 2 is a signal waveform diagram of each part, Fig. 3 is a signal waveform diagram when a sine wave is used in the case of the present invention, and Fig. 4 is a conventional circuit configuration. It is a diagram. 6: Fixed level giving circuit, 8: Comparator.
Claims (1)
て、入力信号を遅延させる遅延回路を設け、この遅延回
路の出力を前記コンパレータの比較基準として用いるこ
とを特徴とする波形整形回路。 2)コンパレータを使用して波形整形を行う回路におい
て、入力信号を遅延させる遅延回路と、この遅延回路の
出力を結果的に圧縮する固定レベル付与回路とを設け、
この固定レベル付与回路の出力を前記コンパレータの比
較基準として用いることを特徴とする波形整形回路。[Claims] 1) A waveform shaping circuit that uses a comparator to perform waveform shaping, characterized in that a delay circuit that delays an input signal is provided, and the output of this delay circuit is used as a comparison reference for the comparator. circuit. 2) In a circuit that performs waveform shaping using a comparator, a delay circuit that delays an input signal and a fixed level imparting circuit that compresses the output of this delay circuit are provided,
A waveform shaping circuit characterized in that the output of the fixed level imparting circuit is used as a comparison standard for the comparator.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21830585A JPS6277715A (en) | 1985-09-30 | 1985-09-30 | Waveform shaping circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21830585A JPS6277715A (en) | 1985-09-30 | 1985-09-30 | Waveform shaping circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6277715A true JPS6277715A (en) | 1987-04-09 |
Family
ID=16717756
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21830585A Pending JPS6277715A (en) | 1985-09-30 | 1985-09-30 | Waveform shaping circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6277715A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02239752A (en) * | 1989-02-03 | 1990-09-21 | Digital Equip Corp <Dec> | Transmission of high band width signal through coaxial cable |
US5210397A (en) * | 1990-05-03 | 1993-05-11 | Psc, Inc. | Differentiating and integrating circuit for translating bar code signals into corresponding pulses |
US5359238A (en) * | 1992-08-04 | 1994-10-25 | Ford Motor Company | Analog to digital interface circuit with internal resistance compensation and integrity verification |
US5471167A (en) * | 1993-08-13 | 1995-11-28 | Motorola, Inc. | Circuit for use with a feedback arrangement |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50120955A (en) * | 1974-03-09 | 1975-09-22 | ||
JPS5225531A (en) * | 1975-08-21 | 1977-02-25 | Fuji Electric Co Ltd | Integration type floating comparator |
-
1985
- 1985-09-30 JP JP21830585A patent/JPS6277715A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50120955A (en) * | 1974-03-09 | 1975-09-22 | ||
JPS5225531A (en) * | 1975-08-21 | 1977-02-25 | Fuji Electric Co Ltd | Integration type floating comparator |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02239752A (en) * | 1989-02-03 | 1990-09-21 | Digital Equip Corp <Dec> | Transmission of high band width signal through coaxial cable |
US5210397A (en) * | 1990-05-03 | 1993-05-11 | Psc, Inc. | Differentiating and integrating circuit for translating bar code signals into corresponding pulses |
US5359238A (en) * | 1992-08-04 | 1994-10-25 | Ford Motor Company | Analog to digital interface circuit with internal resistance compensation and integrity verification |
US5471167A (en) * | 1993-08-13 | 1995-11-28 | Motorola, Inc. | Circuit for use with a feedback arrangement |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6277715A (en) | Waveform shaping circuit | |
EP0087510A1 (en) | Single shot multivibrator | |
KR890002174Y1 (en) | Puse delay circuit | |
JP2664958B2 (en) | Clock duty adjustment circuit | |
KR950001439Y1 (en) | R-s flip flop | |
JPH0422215A (en) | Pulse width variable circuit | |
JPS5996983U (en) | Signal selection scanning circuit | |
SU1182649A1 (en) | Device for delaying pulses | |
SU1478289A1 (en) | Frequency comparator | |
JPS60111370A (en) | Data extracting circuit | |
JPS58178624A (en) | Phase adjusting circuit of pulse signal | |
JPS5881599U (en) | Reverberation adding device | |
JPS60109133U (en) | semiconductor integrated circuit | |
JPH02145011A (en) | Waveform shaping circuit | |
JPH07160741A (en) | Method for simulating operation delay time of electric circuit | |
JPS6198014A (en) | Noise pulse eliminating device | |
JPS63250758A (en) | Network using microprocessor or the like | |
JPH03212015A (en) | Waveform shaping circuit using microcomputer | |
JPH0424888B2 (en) | ||
JPH0334693B2 (en) | ||
JPH05312607A (en) | Waveform shaping circuit for vortex flowmeter | |
JPS59160316A (en) | Waveform shaping circuit | |
JPS5827777U (en) | Delay time measurement circuit | |
JPS57168317A (en) | Signal separating circuit | |
JPS5956883U (en) | Switching control signal generation circuit for input signal switching circuit in chroma circuit |