JPS6276545A - Drive circuit substrate for display device - Google Patents
Drive circuit substrate for display deviceInfo
- Publication number
- JPS6276545A JPS6276545A JP60214570A JP21457085A JPS6276545A JP S6276545 A JPS6276545 A JP S6276545A JP 60214570 A JP60214570 A JP 60214570A JP 21457085 A JP21457085 A JP 21457085A JP S6276545 A JPS6276545 A JP S6276545A
- Authority
- JP
- Japan
- Prior art keywords
- film
- address
- display device
- line
- drive circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 13
- 239000010408 film Substances 0.000 claims abstract description 52
- 239000010409 thin film Substances 0.000 claims abstract description 21
- 239000010407 anodic oxide Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract 2
- 239000002184 metal Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000010410 layer Substances 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract 2
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000012528 membrane Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000003601 intercostal effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、薄膜トランジスタアレイにより駆動される液
晶等の表示装置の駆動回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a driving circuit board for a display device such as a liquid crystal device driven by a thin film transistor array.
近年、アモルファスの８１や多結晶のＣｄＳ。 In recent years, amorphous 81 and polycrystalline CdS.
ｃｄＳｅなどの半導体１膜を用いた薄膜トランジスタを
スイッチング素子としたアクティブ・７１ヘリクス型の
表示装置が注目されている。薄膜トランジスタアレイは
、ガラス基板等を用いて低温プロセスで形成することが
できるため、安価に大面積の表示装置を実現できるとい
う利点を有する。An active 71-helix type display device that uses a thin film transistor made of a single semiconductor film such as cdSe as a switching element is attracting attention. Thin film transistor arrays can be formed using a glass substrate or the like in a low-temperature process, and therefore have the advantage that a large-area display device can be realized at low cost.
第５図はこの様なアクティブ・マトリクス型の表示装置
の等何回路を示す。図において、Ａ （Ａ１１．Ａｔ
２ 、・・・）はアドレス線、Ｄ （Ｄｌｌ、Ｄ＋ ２
、・・・）は画像信号が供給されるデータ線であり、
これらアドレス線Ａとデータ線りの各交差位置に画素に
対応して薄膜トランジスタＴ （Ｔ１１．Ｔｔ ２ 、
・・・）が形成される。薄膜トランジスタＴのゲート電
極はアドレス線Ａに、ソース電極はデータ線りに、ドレ
イン電極は表示素子Ｓ （Ｓ１ｔ 、 Ｓｔ ２ 、・
・・）の画素電極にそれぞれ接続されている。表示素子
Ｓとしては、液晶素子、エレクトロルミネセンス（ＥＬ
）素子、エレクトロクロミック素子等が用いられる。表
示素子Ｓとして液晶素子を用いる場合通常、図示のよう
に駆動電圧を保持するためのキャパシタＣ（Ｃｔ １．
Ｃｔ ２ 、・・・）が設けられる。アドレスＦＡＡ、
データ線り、ｉｌｌ！トランジスタＴ１キャパシタＣお
よび表示素子Ｓの画素電極は絶縁性基板上に集積形成さ
れて駆動回路基板構成する。そしてこの駆動回路基板と
対向電極が形成された透明基板の間に液晶層を挟持する
ことにより、アクティブ・マトリクス型液晶表示装置が
得られる。なお、薄膜トランジスタＴのオフ抵抗および
表示素子の抵抗が充分に高い場合には、キャパシタＣを
必要としない。FIG. 5 shows a circuit diagram of such an active matrix type display device. In the figure, A (A11.At
2,...) are address lines, D (Dll, D+ 2
,...) are data lines to which image signals are supplied,
Thin film transistors T (T11.Tt 2 ,
) is formed. The gate electrode of the thin film transistor T is connected to the address line A, the source electrode is connected to the data line, and the drain electrode is connected to the display element S (S1t, St2, .
...) are respectively connected to the pixel electrodes. As the display element S, a liquid crystal element, an electroluminescent (EL)
) elements, electrochromic elements, etc. are used. When a liquid crystal element is used as the display element S, a capacitor C (Ct 1.
Ct 2 , . . . ) are provided. Address FAA,
Data line ill! The transistor T1 capacitor C and the pixel electrode of the display element S are integrally formed on an insulating substrate to constitute a driving circuit board. By sandwiching a liquid crystal layer between this drive circuit board and a transparent substrate on which a counter electrode is formed, an active matrix type liquid crystal display device can be obtained. Note that if the off-resistance of the thin film transistor T and the resistance of the display element are sufficiently high, the capacitor C is not required.
この種の表示装置を高精細あるいは大面積に実現する場
合には、用いる薄膜トランジスタの数が非常に多くなる
。例えば、アドレス４００×データ４００の場合、素子
数は１６００００となる。When realizing this type of display device with high definition or a large area, the number of thin film transistors used becomes extremely large. For example, in the case of 400 addresses x 400 data, the number of elements is 160,000.
この様な多数の薄膜トランジスタアレイを完全に製作す
ることは困難であり、種々の欠陥が発生する。その原因
としては、（１）多層配線間あるいはキャパシタの電気
的短絡、（２）配線の解放、（３）薄膜トランジスタの
欠陥、等がある。表示装置として点欠陥を許容した場合
、配線の解放は容易に救済することができる。例えばア
ドレス線が途中の一点で断線した場合には、アドレス線
の両方から信号を供給するようにすることにより、救済
できる。またキャパシタは、薄膜トランジスタのオフ抵
抗を充分に大きくし液晶の抵抗率を上げれば設ける必要
がないため、この部分７″′致命的な欠陥とならない。It is difficult to completely manufacture such a large number of thin film transistor arrays, and various defects occur. The causes include (1) electrical short circuits between multilayer interconnects or capacitors, (2) open interconnects, and (3) defects in thin film transistors. If a point defect is tolerated in the display device, it can be easily repaired by opening the wiring. For example, if an address line is broken at one point on the way, it can be repaired by supplying signals from both address lines. Furthermore, since it is not necessary to provide a capacitor if the off-resistance of the thin film transistor is sufficiently increased and the resistivity of the liquid crystal is increased, this portion 7'' does not become a fatal defect.
しかし、配線の短絡事故は致命的な大きい欠陥となる。However, a short-circuit accident in the wiring can be a major, fatal defect.
たとえばアドレス線とデータ線が短絡すると、これらの
配線に沿って線欠陥となる。しかもこの短絡は簡単には
補修により救済することができない。For example, if an address line and a data line are shorted, a line defect will occur along these lines. Moreover, this short circuit cannot be easily relieved by repair.
この様な多層配線間の短絡を防止する方法として、アド
レス線兼ゲートＮ極を例えばＴａｇ！により形成してそ
の表面に陽極酸化膜を形成し、更にその上にＳｉＯ２膜
またはＳｉ：＋Ｎ＋膜を堆積するという、グー１〜絶縁
膜を２層構造とすることが提案されている（特公昭６０
−５４４７８号公報）。しかしこの方法では、Ｔａ膜の
陽極酸化によりアドレス線の抵抗が大きくなってしまう
。例えば、２２０Ｘ２４０画素で４４ｍｍＸ６０ｍｔｎ
の画面をつくる薄膜トランジスタアレイを考える。As a method to prevent such short circuits between multilayer wiring, for example, Tag! It has been proposed to form the insulating film into a two-layer structure by forming an anodized film on the surface of the insulating film, and then depositing a SiO2 film or a Si:+N+ film on top of the anodic oxide film. 60
-54478). However, in this method, the resistance of the address line increases due to anodic oxidation of the Ta film. For example, 44mmX60mtn with 220X240 pixels
Consider a thin film transistor array that creates a screen.
１５００人のＴａ１ｌで配線抵抗的６０にΩのアドレス
線を表面から約７００人酸化すると、配線抵抗は約１１
０にΩになる。このように配線抵抗が大きくなると、ア
ドレスパルスの遅延による波形歪みが大きくなる。この
結果アドレス線の信号入力端部と終端部での画素への書
込みに差が生じ画質の均一性が大きく損われることにな
る。Ｔａ膜の膜厚を大きくすれば配線抵抗を小さくする
ことができるが、余り厚くすると膜の剥がれやデータ線
の断線の原因となる。When an address line with a wiring resistance of 60Ω is oxidized from the surface by about 700 people with Ta1l of 1500 people, the wiring resistance becomes about 11
becomes Ω to 0. When the wiring resistance increases in this way, waveform distortion due to address pulse delay increases. As a result, there is a difference in writing to pixels at the signal input end and the terminal end of the address line, resulting in a significant loss of uniformity in image quality. If the thickness of the Ta film is increased, the wiring resistance can be reduced, but if it is made too thick, it may cause peeling of the film or disconnection of the data line.
また、Ｔａ膜によるアドレス線およびゲート電極を形成
し、その上にＳｉＯ２，ｔｌｌを堆積した後、Ｓ ｉ
０２ ＭＡのピンホール部のみをピンホールを介して陽
極酸化する方法も考えられている（特公昭６０−５４４
７８号公報）。しかしこの方法は、その後に３ｉ０２膜
に孔が開いた場合に多層配線間の短絡を生じるため、短
絡防止策として不充分である。In addition, after forming address lines and gate electrodes using a Ta film and depositing SiO2 and tll on them, Si
02 A method of anodizing only the pinhole portion of MA through the pinhole has been considered (Japanese Patent Publication No. 60-544).
Publication No. 78). However, this method is insufficient as a measure to prevent short circuits since short circuits occur between multilayer interconnections when holes are subsequently formed in the 3i02 film.
本発明は上記した点に鑑みなされたもので、配線抵抗を
大きくすることなく多層配線間の短絡を確実に防止し、
もって優れた画像表示を可能とする表示装置用駆動回路
基板を提供することを目的とする。The present invention was made in view of the above points, and it reliably prevents short circuits between multilayer wiring without increasing wiring resistance.
An object of the present invention is to provide a drive circuit board for a display device that enables excellent image display.
本発明は、絶縁性基板上に所定の金属膜によりアドレス
線およびゲート電極を形成し、この上に絶縁膜を介して
アドレス線と交差するデータ線を形成し、アドレス線と
データ線の各交差位置には薄膜トランジスタを配置する
表示装置用駆動回路基板において、前記アドレス線のデ
ータ線と交差する位置およびゲート電極表面にのみ選択
的に陽極酸化膜を形成し、これらの部分のみを２層の絶
縁膜構造とする。The present invention forms address lines and gate electrodes using a predetermined metal film on an insulating substrate, forms data lines that intersect with the address lines through an insulating film, and forms each intersection of the address line and the data line. In a display drive circuit board in which thin film transistors are arranged, an anodic oxide film is selectively formed only at the positions where the address line intersects with the data line and on the gate electrode surface, and only these parts are covered with two layers of insulation. It has a membrane structure.
本発明によれば、層間絶縁膜を陽極酸化膜を含む２層絶
縁膜構造とすることにより、多層配線間の短絡を確実に
防止することができる。しがも陽極酸化膜を設けるのは
アドレス線の一部およびゲート電極部分のみであるため
、アドレス線の高抵抗化を招くことはない。従って本発
明によれば、信頼性が高く、かつ優れた表示画像が得ら
れる表示装置用駆動回路基板が実現する。According to the present invention, by forming the interlayer insulating film into a two-layer insulating film structure including an anodic oxide film, short circuits between multilayer interconnections can be reliably prevented. However, since the anodic oxide film is provided only on a portion of the address line and the gate electrode portion, the resistance of the address line does not increase. Therefore, according to the present invention, a drive circuit board for a display device that is highly reliable and provides an excellent display image is realized.
以下本発明の詳細な説明する。 The present invention will be explained in detail below.
第１図（ａ）〜（Ｃ）は一実施例の駆動回路基板であり
、（ａ）は平面図、（ｂ）および（ｃ）はそれぞれ（ａ
）のＡ−Ａ−およびＢ−８−断面図である。具体的には
４４ｍＸ６０ｍの画面の液晶表示装置用として構成され
たものである。これを製造工程に従って説明すると、絶
縁性基板として例えばコーニング７０５９などのガラス
基板１を用い、先ずこの上にＴａ１ｌを１５００人スパ
ッタし、これをパターン形成したアドレス線２およびこ
れから突設した形のゲート電極３を形成する。FIGS. 1(a) to (C) are drive circuit boards of one embodiment, where (a) is a plan view, and (b) and (c) are (a), respectively.
) are AA- and B-8 cross-sectional views. Specifically, it is configured for use in a liquid crystal display device with a screen of 44 m x 60 m. To explain this according to the manufacturing process, a glass substrate 1 such as Corning 7059 is used as an insulating substrate, 1,500 Ta1l is sputtered thereon, and a pattern is formed on the address line 2 and a gate protruding from it. Electrode 3 is formed.
次にフォトレジストパターンを形成し、１００Ｖの電圧
で露出している７層膜表面を陽極酸化して、ゲート電極
３上およびアドレス線２のうち後にデータ線が交差する
部分（第１図（ａ）に斜線を施して示した領域）上に選
択的に陽極酸化膜４（４１，４２）を形成する。この後
全面にプラズマＣｖＤにより２５００人のＳｉ○２膜５
を堆積し、続いて半導体簿膜としてアンドープのアモル
ファス３ｉ（ａ−８ｉ）膜６とｎ＋型ａ−３ｉ膜７を堆
積し、第１図（ａ）に破線で囲んだ領域にこれらの半導
体簿膜を島状に残すようにパターン形成する。次にＩＴ
Ｏ膜を１５００人スパッタし、これをパターン形成して
画素電極８を形成する。Next, a photoresist pattern is formed, and the exposed 7-layer film surface is anodized with a voltage of 100V, and the portions on the gate electrode 3 and the address line 2 where the data line intersects later (Fig. 1(a) The anodic oxide film 4 (41, 42) is selectively formed on the shaded area (). After this, 2,500 Si○2 films 5 were applied to the entire surface by plasma CVD.
Then, an undoped amorphous 3i (a-8i) film 6 and an n+ type a-3i film 7 are deposited as semiconductor films, and these semiconductor films are deposited in the area surrounded by the broken line in FIG. 1(a). A pattern is formed so that the film remains in the form of islands. Next, IT
1500 O films are sputtered and patterned to form pixel electrodes 8.
そしてへ２膜を１μｍ蒸着し、パターニングしてデータ
線９、これから突設した形のソース電極１０および画素
電極８に接続されるドレイン電極１１を形成する。最後
に薄膜トランジスタのチャネル領域部のｎ＋型ａ−８ｉ
膜７をＣＤＥ法により除去する。Then, a 1 .mu.m thick film is deposited and patterned to form the data line 9, the source electrode 10 protruding from the data line 9, and the drain electrode 11 connected to the pixel electrode 8. Finally, the n+ type a-8i in the channel region of the thin film transistor.
Film 7 is removed by CDE method.
本実施例では、アドレス線の抵抗は陽（唄酸化前の値６
０ ｋΩに対して６６にΩであり、その増加は殆ど問題
にならない。またアドレスパルスの遅延は全面陽極酸化
した場合の約１／２に止まり、従って表示のばらつきが
少なくなる。In this example, the resistance of the address line is positive (the value before oxidation is 6).
It is 66 Ω compared to 0 kΩ, and the increase is hardly a problem. Further, the delay of the address pulse is only about half that of the case where the entire surface is anodized, and therefore the display variation is reduced.
第２図は別の実施例の要部構成を第１図（ａ）に対応さ
せて示す。先の実施例と対応する部分には同一符号を付
して詳細な説明は省略する。先の実施例では、アドレス
線から突設する形でゲート電極を形成したのに対して、
この実施例ではアドレス線上に薄膜トランジスタを構成
している。このような構成の場合にも、アドレス線２上
およびゲート電極３上に斜線を施して示したように選択
的に陽極酸化１４ （４ｔ 、 ４２ ）を形成するこ
とにより、先の実施例と同様の効果が得られる。FIG. 2 shows the main structure of another embodiment in correspondence with FIG. 1(a). Portions corresponding to those in the previous embodiment are designated by the same reference numerals and detailed explanations will be omitted. In the previous embodiment, the gate electrode was formed to protrude from the address line.
In this embodiment, thin film transistors are formed on the address lines. Even in the case of such a structure, by selectively forming the anodic oxide 14 (4t, 42) on the address line 2 and the gate electrode 3 as indicated by hatching, the same process as in the previous embodiment can be achieved. The effect of this can be obtained.
第３図（ａ）（ｂ）は更に他の実施例の要部構成を示す
平面図とそのＣ−Ｃ−断面図である。ここでも先の実施
例と対応する部分には同一符号を付してあり、詳細な説
明は省略する。この実施例が第１図の実施例と異なる点
は、アドレス線２のうち陽極酸化されていない部分で酸
化！１１５にできるだけ大きい開口を開けて、アドレス
線２にコンタクトする金属配線１２を積層していること
である。これにより、アドレス線のより一層の低抵抗化
が図られる。具体的に金爲配線１２として１μｍのＡ℃
配線を用いて、アドレス線の抵抗を約２０にΩにまで低
下させることができた。FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along the line C--C of still another embodiment. Here too, parts corresponding to those in the previous embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The difference between this embodiment and the embodiment shown in FIG. 1 is that the portions of the address lines 2 that are not anodized are oxidized! The metal wiring 12 contacting the address line 2 is laminated by making an opening as large as possible in the address line 115. This makes it possible to further reduce the resistance of the address line. Specifically, the temperature of the metal wiring 12 is 1 μm A°C.
Using wiring, it was possible to reduce the resistance of the address lines to about 20 Ω.
第４図（ａ）（ｂ）は、第３図の実施例を変形した実施
例の平面図とそのＤ−Ｄ−断面図である。4(a) and 4(b) are a plan view and a cross-sectional view taken along the line DD of the embodiment shown in FIG. 3, which is modified from the embodiment shown in FIG.
この実施例では、アドレス線２にコンタクトさせて重ね
る金属配置！Ｊ１３を、アドレス線２に沿って連続的に
配設している。従ってこの金属配線１３とデータｔｉａ
９の絶縁のためにデータ線９上に約１μ雇のポリイミド
膜１４を設けている。この実施例の場合更にアドレス線
の低抵抗化が可能であり、金属配線１３として１μ卯の
へλ膜を用いて約１にΩのアドレス線抵抗が実現できた
。In this embodiment, the metal arrangement is overlapped in contact with the address line 2! J13 are continuously arranged along the address line 2. Therefore, this metal wiring 13 and data tia
A polyimide film 14 with a thickness of about 1 μm is provided on the data line 9 for insulation of the data line 9. In this embodiment, it is possible to further reduce the resistance of the address line, and by using a 1 μm thick λ film as the metal wiring 13, an address line resistance of approximately 1Ω was achieved.
第３図および第４図の実施例のようにアドレス線に更に
金属配線を積み重ねる場合、本発明の構造では１ｌｆｆ
ｉ酸化膜が部分的に形成されていて、コンタクト孔形成
のためのエツチングはＳ ｉ ０２ Ｉ！Ｊに対しての
み行なえばよく、エツチングの困難なＴａＯに対しては
必要でないので、工程が容易である。When metal wiring is further stacked on the address line as in the embodiments of FIGS. 3 and 4, in the structure of the present invention, 1lff
The i oxide film is partially formed, and the etching for forming the contact hole is S i 02 I! The process is easy because it is necessary to perform etching only on J and not on TaO, which is difficult to etch.
本発明は上記した実施例に限られるものではない。例え
ばアドレス線を構成する金属膜はＴａに限らず、Ｔｉ、
Ａｎなど陽極酸化できるものであればよい。１ＪＩＩｌ
トランジスタを構成する半導体薄膜もａ−８ｉに限らず
、多結晶３ｉやＣｄＳｅ。The present invention is not limited to the embodiments described above. For example, the metal film constituting the address line is not limited to Ta, but also Ti,
Any material that can be anodized, such as An, may be used. 1JIIl
The semiconductor thin film that constitutes the transistor is not limited to A-8i, but also polycrystalline 3i and CdSe.
ＣｄＳなどを用いることができる。肋間絶縁膜としても
、ＳｉＯ２膜の伯、３ｉ３Ｎ４ｇ！やＡＱ２０１膜等を
用いることができる１、その池水発明はその趣旨を逸脱
しない鞘囲で種々変形して実施することができる。CdS or the like can be used. 3i3N4g, the best SiO2 film, can also be used as an intercostal insulation film! or AQ201 membrane, etc.1, and the pond water invention can be implemented with various modifications in the sheath without departing from its spirit.
第１図（ａ）〜＜Ｃ）は本発明の一実施例の駆動回路基
板を示す図、第２図は他の実施例の駆動回路基板の要部
構成を示す図、第３図（ａ）（ｂ）および第４図（ａ）
（ｂ）は更に他の実施例の駆動回路基板の要部構成を示
す図、第５図はアクティブ・マトリクス型液晶表示装置
の等価回路を示す図である。
１・・・ガラス基板、２・・・アドレス線（Ｔａ膜）、
３・・・ゲート電極（Ｔａｌｌ＞、４ （４ｔ 、４２
）−陽極酸化膜、５・・・ＣＶＤ５ ｉ ０２膜、６
・・・ａ−３ｉ躾、７・・・ｎゝ型ａ−８ｉ膜、８・・
・画素電極、９・・・データ線＜ＡＲＩＩＩ）、１０・
・・ソース１ｔｆｉ（ＡＮ膜）、１１・・・ドレイン１
！楊（ＡパＩ、１２．１３・・・金属配線、１４・・・
ポリイミド膜。
出願人代理人 弁理士 鈴江武彦
第１図
第１図
第２図
第３図
第４図1(a) to <C) are diagrams showing a drive circuit board according to one embodiment of the present invention, FIG. 2 is a diagram showing the main part configuration of a drive circuit board according to another embodiment, and FIG. )(b) and Figure 4(a)
(b) is a diagram showing the main part configuration of a drive circuit board of still another embodiment, and FIG. 5 is a diagram showing an equivalent circuit of an active matrix type liquid crystal display device. 1...Glass substrate, 2...Address line (Ta film),
3... Gate electrode (Tall>, 4 (4t, 42
)-anodized film, 5...CVD5 i02 film, 6
...a-3i discipline, 7...n type a-8i membrane, 8...
・Pixel electrode, 9...data line <ARIII), 10・
... Source 1tfi (AN film), 11... Drain 1
! Yang (A Pa I, 12.13...metal wiring, 14...
Polyimide membrane. Applicant's Representative Patent Attorney Takehiko SuzueFigure 1Figure 1Figure 2Figure 3Figure 4
Claims (3)
アドレス線と、このアドレス線が形成された基板上にア
ドレス線と交差する方向に形成された複数本のデータ線
と、これらアドレス線とデータ線の各交差位置に形成さ
れた複数の薄膜トランジスタと、これらの薄膜トランジ
スタを介して選択的に前記データ線に接続されて表示素
子に駆動電圧を印加する複数の画素電極とを有し、前記
薄膜トランジスタのゲート電極およびソース電極がそれ
ぞれ前記アドレス線およびデータ線と一体形成され、ド
レイン電極が前記画素電極に接続されて構成される表示
装置用駆動回路基板において、前記アドレス線のうち前
記データ線と交差する部分および前記ゲート電極の表面
に前記アドレス線およびゲート電極を構成する金属の陽
極酸化膜を設けたことを特徴とする表示装置用駆動回路
基板。(1) An insulating substrate, a plurality of address lines formed on this substrate, a plurality of data lines formed on the substrate on which these address lines are formed in a direction intersecting the address lines, and these lines. The display device includes a plurality of thin film transistors formed at each intersection of an address line and a data line, and a plurality of pixel electrodes that are selectively connected to the data line via these thin film transistors and apply a driving voltage to the display element. , a drive circuit board for a display device configured such that a gate electrode and a source electrode of the thin film transistor are integrally formed with the address line and the data line, respectively, and a drain electrode is connected to the pixel electrode; 1. A drive circuit board for a display device, characterized in that a metal anodic oxide film constituting the address line and the gate electrode is provided on a portion intersecting the line and on the surface of the gate electrode.
請求の範囲第１項記載の表示装置用駆動回路基板。(2) The drive circuit board for a display device according to claim 1, wherein the semiconductor thin film is an amorphous Si film.
部分にコンタクトしてアドレス線の抵抗を低減するため
の金属配線が形成されている特許請求の範囲第１項記載
の表示装置用駆動回路基板。(3) A drive circuit for a display device according to claim 1, wherein a metal wiring is formed for contacting a portion of the address line where the anodic oxide film is not formed to reduce the resistance of the address line. substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60214570A JPS6276545A (en) | 1985-09-30 | 1985-09-30 | Drive circuit substrate for display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60214570A JPS6276545A (en) | 1985-09-30 | 1985-09-30 | Drive circuit substrate for display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6276545A true JPS6276545A (en) | 1987-04-08 |
| JPH0340511B2 JPH0340511B2 (en) | 1991-06-19 |
Family
ID=16657900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60214570A Granted JPS6276545A (en) | 1985-09-30 | 1985-09-30 | Drive circuit substrate for display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6276545A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02216129A (en) * | 1989-02-17 | 1990-08-29 | Matsushita Electric Ind Co Ltd | Liquid crystal image display device and production thereof |
| US5146301A (en) * | 1987-10-15 | 1992-09-08 | Sharp Kabushiki Kaisha | Terminal electrode structure of a liquid crystal panel display |
| US5485019A (en) * | 1992-02-05 | 1996-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6839098B2 (en) * | 1987-06-10 | 2005-01-04 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154289A (en) * | 1978-05-26 | 1979-12-05 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor array |
-
1985
- 1985-09-30 JP JP60214570A patent/JPS6276545A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154289A (en) * | 1978-05-26 | 1979-12-05 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor array |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6839098B2 (en) * | 1987-06-10 | 2005-01-04 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US6992744B2 (en) | 1987-06-10 | 2006-01-31 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US7196762B2 (en) | 1987-06-10 | 2007-03-27 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US7450210B2 (en) | 1987-06-10 | 2008-11-11 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US5146301A (en) * | 1987-10-15 | 1992-09-08 | Sharp Kabushiki Kaisha | Terminal electrode structure of a liquid crystal panel display |
| JPH02216129A (en) * | 1989-02-17 | 1990-08-29 | Matsushita Electric Ind Co Ltd | Liquid crystal image display device and production thereof |
| US5485019A (en) * | 1992-02-05 | 1996-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US5849611A (en) * | 1992-02-05 | 1998-12-15 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a taper shaped contact hole by oxidizing a wiring |
| US6147375A (en) * | 1992-02-05 | 2000-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
| US6476447B1 (en) | 1992-02-05 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device including a transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0340511B2 (en) | 1991-06-19 |
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