JPS6276537A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a via hole having a side wall with a smoothly curved slope by one process by making an interlayer insulative film made of the same material have a change in a composite ratio in advance whereby the film itself has a difference in an etching rate. CONSTITUTION:In a semiconductor device 1 wherein a variety of circuit elements are formed on a semiconductor substrate and covered by an insulative film, a lower layer wiring is formed thereon and an interlayer insulative film 3 composed of a silicon oxynitride is formed on the lower layer wiring by introducing ammonia, silane and nitrous oxide gases by a plasma CVD. A resist 4 is applied thereto and an ordinary etching is conducted, for example, through a reactive ion etching. Thus, a via hole 6 having a side wall automatically formed with a smoothly curved slope can be obtained by one etching due to a difference in an etching rate.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device.
The present invention relates to a method for forming Hole).

[Conventional technology]

A peer hole is a phenomenon that occurs as semiconductor devices become more integrated.
It refers to a hole formed in an interlayer insulating film for connection between layers, which has become necessary due to multilayer wiring, and has a structure as shown by reference numeral (6) in the cross-sectional view of FIG. If the step of the pier hole (6) is steep, as shown in Figure 5, the thickness of the upper layer wiring Q will be thinner in the part (), resulting in higher resistance or poor coverage, which may cause wire breakage. This becomes a problem and lacks credibility, so it is necessary for this pier hole to have a slope in the mlJ wall as shown in Figure 4 (6).

FIG. 3 shows a typical manufacturing process for a peer hole for connecting multilayer interconnections in a large-scale integrated circuit, and will be used hereinafter to explain the conventional method.

As shown in Fig. 3, there is a resist where the opening is to be made in the interlayer insulating film (13).
4) '! Etching is performed halfway through the entire process using normal isotropic etching. Next, as shown in Figure 3 fb+, etching is performed by anisotropic etching with a downward direction in the figure until it reaches the lower layer wiring (2). )+4)'i by removing 1ll1111? A pier hole (6) with a slope is obtained. Finally, as shown in FIG. 3 1dl, the upper layer wiring (5) is completely formed to obtain the upper layer wiring which is ohmically connected to the lower layer wiring (2).

[Problem that the invention seeks to solve]

In conventional semiconductor devices, two steps of etching are required to obtain a pier hole with a sloped sidewall.

There is also a manufacturing method in which two or more layers of insulating films with different etching rates are stacked, but this method requires the same etching, but requires a two-step process after forming the insulating film. Furthermore, in both cases, the formed pier holes are not smooth and have steps. This may cause a problem in coverage at the step portion when forming the upper layer wiring.

This invention was made to solve the above-mentioned problems, and it is a semiconductor device in which a peer hole with a smooth slope on the side wall is formed in an interlayer insulating film using a single process for forming an insulating film and etching. The purpose is to write the complete method for manufacturing the device.

[Means for solving problems]

In the method for manufacturing a semiconductor device according to the present invention, when forming an interlayer insulating film, the composition ratio of the interlayer insulating film made of the same material is varied in advance so that the film itself has a certain etching rate. As a result, a pier hole with a smooth slope on the side wall can be obtained by performing film formation and etching in one process.

[Effect]

In the VC of the present invention, an insulating material such as silicon oxynitride, whose etching rate can be changed by changing the composition ratio by process control during formation, is used as the interlayer insulating film. When forming an interlayer insulating film using this insulating material, the glabellar insulating film is formed by changing the composition ratio of the material so that the etching rate increases from the lower layer to the upper layer.

When a pier hole is formed in the interlayer insulating film formed in this manner, a pier hole having a smooth slope that expands upward is formed in one etching step depending on the above-mentioned etching rate.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. Figure 1: A semiconductor device Il in which various circuit elements are formed on a semiconductor substrate and an insulating film is formed over the entire semiconductor substrate.
+ indicates the state in which lower layer wiring is formed on it,
On top of this, plasma CV D (Chemical Va
Ammonia (N
H4) gas, silane (SiH4) gas.

Figure 1+1)l by introducing nitrous oxide (NtO) gas
An interlayer insulating film (3) made of silicon oxynitride shown as Ic is completely formed. Silicon oxynitride film (
In the formation of 3), as shown in Figure 2 (8L1), as the flow rate of nitrous oxide gas increases during film formation, that is, the amount of oxygen in the silicon oxynitride film that is formed, the etching rate increases. It is known that
Ru. Therefore, when forming a silicon oxynitride film by plasma CVD, the flow rate of nitrous oxide gas is
As shown in Figure (bl), the silicon oxynitride film formed by increasing the etching rate continuously (31) has the property that the etching rate is lower at the bottom and increases as it goes up. If the resist +4)i is applied as shown in Figure 1 (0) and normal etching is performed, for example by reactive ion etching, the difference in etching rate will automatically result in one etching process as shown in Figure 1 (1). A pier hole (6) with a smooth slope on the side wall is obtained as shown in Figure 1.Finally, as shown in Fig. 1, the resist (4) is removed and the upper layer aluminum wiring (6) is completely formed to form a multilayer wiring. is obtained.

Although the above description has been made using silicon oxynitride as the interlayer insulating film, other metals made of materials whose shearing rate can be changed by changing the composition ratio during the formation of the interlayer insulating film may also be used. has the same effect.

〔Effect of the invention〕

As described above, according to the present invention, in a method of manufacturing a semiconductor device for forming peer holes for multilayer wiring, a material is used as an interlayer insulating film, and the etching rate can be changed by changing the component ratio during formation. Since we formed an insulating film with a variable etching rate using an insulating film consisting of the following, it is possible to obtain a via hole with a slope on the picture wall by one-time etching.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a characteristic diagram for explaining the effects of the invention, and FIG. 3 is a diagram showing a conventional manufacturing process of a semiconductor device. FIG. 4 is a cross-sectional view of a semiconductor device having a general multilayer wiring structure, and FIG. 5 is a cross-sectional view showing the shape of upper layer wiring in a pier hole with no slope on the side wall. Il+ is a semiconductor device, (2) is a lower layer wiring, +31 f'
(i) silicon oxynitride interlayer insulating film, (4) halide resist, (5) upper layer interconnection, and (6) peer hole. In addition, in the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (4)

[Claims] (1) In a method of manufacturing a semiconductor device having a multilayer wiring structure, a step of forming an interlayer insulating film using the same material but with a different composition ratio so that the etching rate of the upper layer is higher than that of the lower layer; Via holes in the membrane
1. A method for manufacturing a semiconductor device, comprising the step of opening a hole. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is silicon oxynitride (SioN). (3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the composition ratio of the interlayer insulating film changes continuously in the thickness direction of the film. (4) The silicon oxynitride film is formed by CVD, and the composition ratio of the silicon oxynitride is changed by controlling the flow rate of the introduced gas during the formation. 4. A method for manufacturing a semiconductor device according to any one of Item 3.