JPS6275844A - 命令プリフェッチ方法 - Google Patents

命令プリフェッチ方法

Info

Publication number
JPS6275844A
JPS6275844A JP60217077A JP21707785A JPS6275844A JP S6275844 A JPS6275844 A JP S6275844A JP 60217077 A JP60217077 A JP 60217077A JP 21707785 A JP21707785 A JP 21707785A JP S6275844 A JPS6275844 A JP S6275844A
Authority
JP
Japan
Prior art keywords
instruction
operand
processing unit
ipu
instruction processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60217077A
Other languages
English (en)
Japanese (ja)
Other versions
JPH056893B2 (enExample
Inventor
Kunihiro Torikawa
酉川 晋宏
Katsuyuki Iwata
勝行 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60217077A priority Critical patent/JPS6275844A/ja
Publication of JPS6275844A publication Critical patent/JPS6275844A/ja
Publication of JPH056893B2 publication Critical patent/JPH056893B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP60217077A 1985-09-30 1985-09-30 命令プリフェッチ方法 Granted JPS6275844A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60217077A JPS6275844A (ja) 1985-09-30 1985-09-30 命令プリフェッチ方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60217077A JPS6275844A (ja) 1985-09-30 1985-09-30 命令プリフェッチ方法

Publications (2)

Publication Number Publication Date
JPS6275844A true JPS6275844A (ja) 1987-04-07
JPH056893B2 JPH056893B2 (enExample) 1993-01-27

Family

ID=16698467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60217077A Granted JPS6275844A (ja) 1985-09-30 1985-09-30 命令プリフェッチ方法

Country Status (1)

Country Link
JP (1) JPS6275844A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04211827A (ja) * 1990-02-27 1992-08-03 Matsushita Electric Ind Co Ltd デジタルプロセッサ
JPH05100849A (ja) * 1991-10-04 1993-04-23 Fujitsu Ltd バツフア記憶制御方式

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5697146A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Instruction fetch control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5697146A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Instruction fetch control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04211827A (ja) * 1990-02-27 1992-08-03 Matsushita Electric Ind Co Ltd デジタルプロセッサ
JPH05100849A (ja) * 1991-10-04 1993-04-23 Fujitsu Ltd バツフア記憶制御方式

Also Published As

Publication number Publication date
JPH056893B2 (enExample) 1993-01-27

Similar Documents

Publication Publication Date Title
EP0690371B1 (en) Fetch and store buffer for supporting out of order execution in a data processing system
US6298424B1 (en) Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation
US6553487B1 (en) Device and method for performing high-speed low overhead context switch
EP0162778A2 (en) Instruction prefetch system for conditional branch instruction for central processor unit
KR100335785B1 (ko) 데이타처리명령의실행
JPS59100964A (ja) ディスク制御システム及びその並列データ転送方法
US5784711A (en) Data cache prefetching under control of instruction cache
US6237066B1 (en) Supporting multiple outstanding requests to multiple targets in a pipelined memory system
JPH07104841B2 (ja) 多重処理システムの割込み制御方法
US6247101B1 (en) Tagged access synchronous bus architecture
JPH01175634A (ja) データ処理装置
US5598574A (en) Vector processing device
JP2005056401A (ja) キャッシュ可能なdma
US6738837B1 (en) Digital system with split transaction memory access
EP0220990B1 (en) Buffer storage control system
JPH0564825B2 (enExample)
JPS6275844A (ja) 命令プリフェッチ方法
JPH04190435A (ja) マルチプロセッサシステムのメモリアクセス順序保証方式
US20050188155A1 (en) High/low priority memory
JPH02287828A (ja) プリフェッチ制御方式
JPH0285960A (ja) 情報処理システム
JPS61289464A (ja) スカラ演算処理装置
JPS60123944A (ja) 情報処理装置におけるバツフアメモリ制御方式
JPS61145668A (ja) チャネルバッファ制御方法
JPH0298735A (ja) 命令先取り方式