JPS6271091A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To offset coupling noise between a selected word line and a bit line by newly forming a MISFET, and when the memory cell is selected, disconnecting a dummy circuit belonging to the same bit line as the selected memory cell from the bit line. CONSTITUTION:Dummy word lines DW0, DW1 for controlling ON/OFF of MOSFETs T0, T1 are formed and the dummy circuit belonging to the same bit line B1 as the selected memory cell is separated from the bit line B1, so that noise with a phase inverted from coupling noise generated at the selection of the word line W1 is previously generated on the bit line B1. If the size of the MOSFET constituting the memory cell is set up equally to that of the MOSFET constituting the dummy circuit and the level amplitude of the word line W1 and the dummy word line DW1 are set up equally to each other, coupling noises generated on the bit line B1 are offset each other, so that a difference signal between the bit lines B0, B1 which is applied to a sense amplifier SA does not include offset due to the coupling noise.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a dummy circuit for generating a reference level.

(Prior Art) In a conventional semiconductor memory, binary information is read from a memory cell onto a pin line by setting the bit line precharge level to about half of the supply voltage, and at the same time, the bit line is A dynamic ζ-type semiconductor memory that generates a reference level on the other bit line of the pair using a dummy circuit, and amplifies the minute difference signal generated between the bit lines of the pair to the ground level or supply voltage level. Saito et al.
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There is one published in 1985 with 2,521,253 pages.

FIG. 3 shows a circuit diagram of an example of a conventional semiconductor memory of this type, and FIG. 4 shows its operating waveform diagram.

In FIG. 3, the sense amplifier SA is connected to the bit line BO,
The level of Bl is compared, and the level of the bit line with the lower level at this time is lowered to the ground level, while,
The following explanation assumes that the MISFET has the function of raising the level of the higher bit line to the level of the supply voltage VC, and that an N-channel MOSFET is used as the MISFET. .

In FIGS. 3 and 4, when a chip is selected, first the reset signal PO is set to low level and the bit lines BO, B
) are separated. Bit line B O+ B at this time:
The precharge level vO is balanced at nearly half of the supply voltage VC.

Next, word line ν, '0. One of Wl, for example Hwl
is selected and binary information is read from the memory cell onto the pin l-@B1. At this time, the clock signals POO and POL are on the other pin line BO that is paired with the pin line Bl.
This generates an average level of 7 to the sense amplifier SA.

That is, the levels of the clock signals POO and POI are set equal to the bit line precharge level vO before chip selection, and when the reference level is generated, they are changed to the supply power voltage VC level and the ground level, and the reference capacitance CRC'=CS/ 2, just (, CS is the cell capacity f
The optimum reference level is generated by capacitive coupling via k).

Another set of clock signals pio and ptt are bit lines Bl
It is used to generate a reference level on the bit line BO, and when the memory kill connected to the bit line BL is selected, it remains at a level equal to the bit line precharge level VG. When a memory cell is selected, the II reference level is set to bit line B by a level change similar to that of clock signals POO and POI.
Generate on l. At this time, the clock signal FoC.

The level of POI does not change with vO.

Thereafter, the sense amplifier SA is activated by the sense signal SE to amplify the minute difference signals read out on the pins @BO and Bl, thereby setting the bit line level to the ground level and the supply power voltage VC level.

When the chip becomes non-selected, the word line W1 and the clock signals POO and Pot are set to initial levels, that is, the ground level and the vO level, and the sense amplifier SA is deactivated.

Next, the reset signal PO is set to high level and the bit line BO
, Bl are shorted and the levels of bit) iiBO, Bl are balanced. This level becomes the precharge level VO of the bit lines BO and El, and the bit line B immediately before the balance
O.

Since the level of B1 is at the level of the ground voltage and the supply voltage VC, it can be seen that VO=VC,'2.

(Problems to be Solved by the Invention) In the conventional semiconductor memory described above, coupling noise is generated only on one side of the bit line pair from the selected word line via the transfer gate of the selected memory cell, and Since it is added as a positive offset to the read signal from the recell, there is a drawback that the operating margin of the sense amplifier when reading low level information from the upper memory is apparently degraded and narrowed. Furthermore, when the sense amplifier is activated, the capacitance attached to the bit line pair becomes unbalanced by the cell capacitance C8, and the operating margin of the sense amplifier becomes narrow.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory in which capacitance imbalance does not occur between a pair of bit lines when a signal read from a memory cell is amplified by a sense amplifier, and coupling noise generated on the bit lines can be eliminated. It's about doing.

(Means for Solving the Problems) A semiconductor memory of the present invention has bit lines forming rows, word lines forming columns, and information is transferred between and from the bit lines selected by the word lines. memory cells arranged in rows and columns, a sense amplifier with one pair of the bit lines serving as input/output signal lines, and one circuit provided for each bit line f; It maintains the same potential as the precharge level of the line and connects to ground 11 according to the first and second control signals during chip access.
The first and second
a signal line, first and second capacitors connected in series between the first and second signal lines, and a source electrode connected to the bit line at a common connection point of the first and second capacitors. The MI remains in the O state while the Billet 1 electric wire is connected and waiting for chip access.
The dummy circuit includes a SPET and a dummy word line connected to the gate electrode of the MISFET and used to control on/off of the Δ4ISFET.

(Function) A new MISFET is provided to control the connection between the two reference capacitors CB, (=C8/2) and the bit line, and when a memory cell is selected, the same bit as this selected memory cell is connected. By cutting off the connection between the Tabe circuit belonging to the bit line and the bit line, the coupling from the selected word line to the bit line is canceled, and furthermore, the coupling between the selected word line and the bit line is canceled, and the bit line pair constituting all the bit lines during sense amplifier operation is By eliminating the capacitance imbalance between the two, deterioration of the sense amplifier's operational merge is prevented.

(Example) Next, an example of the present invention will be described with reference to the drawings.

The first part is a circuit diagram of one embodiment of the great invention, and the second part is an operation waveform diagram of the semiconductor memory shown in FIG.

The differences between the semiconductor memory shown in FIG. 1 and the conventional semiconductor memory shown in FIG.
The bit 1llBO, Bl and the reference capacitance 0880
Dummy word lines DWO and DWI are inserted between the two to control on/off of MOSFETs TO and Tl, and the number of clock signals for driving the dummy circuit is reduced to two types: POO and POI.

In Fig. 1 and Fig. 2, the input voltage (i) PO and tummy word @DWO, DWI are kept at high level, and all the reference capacitors CR constituting the dummy circuit are set to the same level vO as the bit lines HO and Bl. Next, reset signal I)Q is set to low level and bit line Bo is precharged.
, BL to minute 2 "Dummy War)" line DW1t-Low L'
The MO8f'ETT1 is made non-conductive and the two 1.1 reference capacitors ftc:H.f: are disconnected from the bit line B1 to which the selected memory cell belongs.

At the same time, the selected word line W1 is set to a high level and binary information is read from the memory cell on the bit line 1, the clock signals POO and Pot are set to a low level and a high level, respectively.
A reference level is generated on the bit line BO via a reference capacitor CB of a dummy circuit.

Activate sense amplifier 8A to connect bit line BO.

After amplifying the small difference signal on Bl, the dummy word line DW1, which was previously set to low level, is set to a bright level and the MOSFET is
Tie is made conductive, and the transfer capacitor C in the dummy circuit is connected to the bit line B1.

The subsequent operations are performed in the same manner as in the conventional example described above.

As described above, in this embodiment, by separating the circuit belonging to the same bit line B1 as the selected memory cell from the bit line B1, the coupling that occurs when the word line TV1 is selected can be reduced. A noise having a phase opposite to that of the noise is generated on the bit line l in advance.Here, the sizes of the MOSFETs constituting the memory cell and the dummy circuit are set to 1.<+, and the word '7aw1 and the dummy word @ If the level amplitude of D W ] is carefully set, the coupling noise generated on the bit line L will work to cancel each other out, and as a result, the difference signal between the bit lines BO and B1 applied to the sense amplifier i8A will be does not include the offset due to coupling noise as in the conventional example.

Furthermore, as in the conventional example, if the size of the reference capacitance CF& in the dummy circuit is set to 17'2 of the cell capacitance C8, 1.2CR=C8, and 1 da(-total capacitance in the circuit (2CR) Since the capacitance becomes equal to the cell capacitance C8 in the memory cell, there is no unbalance in the capacitance between the bit lines Bo and BL.Therefore, the operating margin of the sense amplifier SA is increased and the memory cell is smaller than that of a conventional sense amplifier. It becomes possible to amplify the read L7 signal to the positive form.

Please note that the above explanation is for convenience, and all of the explanations are for M of N channel type.
This was done using an example using OSFET, but the BA of this invention is P
A channel type MOSFET or any other insulated gate type transistor can be applied in essentially the same way.

(Effect of the invention) As explained above, the semiconductor memory of the present invention is.

Coupling from the word line to the bit line by separating the dummy circuit belonging to the same pin line as the selected memory from the bit line and making the reference capacitance equal to the cell capacitance. In addition to eliminating deterioration of the sense amplifier operating margin due to the influence of noise, the unbalanced capacitance of the paired bit lines is completely eliminated, and the operating margin of the sense amplifier is increased.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an operating waveform of the semiconductor memory shown in FIG. 1, FIG. 3 is a circuit diagram of an example of a conventional semiconductor memory, and FIG. FIG. 3 is an operation waveform diagram of the semiconductor memory shown in FIG. EO, Bi...Bit line, CB...Reference capacitance, C8...Cell 8k, DWO, L
'WI...Daification-Kude line, PO...
Reset signal to PO. POI...Clock signal, SA...Sense amplifier, vo...Precharge level, w
□, Wl...Word line. Agent Patent Attorney Susumu Uchihara 1-, Yu°-2° 1st Q BO, Bt: Bi, Y column DWOJLWj: Gunko F Dark CB: Pi Kumao) 1CR: Riff 7-Sisis Kan 1n C5; Deru 2 poo, pot: Kuroraf kōgo WO, Wf: Word φgi, Article 2 Figure ゛) D Sai! Qin 3 Figure EO Sen 4 Σ

Claims (1)

[Claims] bit lines forming rows, word lines forming columns, memory cells arranged in rows and columns that are selected by the word lines and transfer information to/from the bit lines; A pair of sense amplifiers are provided as input/output signal lines, and one circuit is provided for each bit line, which maintains the same potential as the precharge level of the bit line while waiting for chip access and outputs first and second control signals during chip access. first and second signal lines that change to a ground potential and a supply power supply potential, respectively, according to the first and second signal lines; first and second capacitors connected in series between the first and second signal lines; A MISFET whose source electrode is connected to the common connection point of the first and second capacitors and whose drain electrode is connected to the bit line and remains on while waiting for chip access; A semiconductor memory comprising: a dummy circuit consisting of a dummy word line for performing off control.