JPH03207079A - Dynamic ram - Google Patents

Abstract

PURPOSE:To amplify high data at high speed and to shorten access time by providing an (n) channel transistor to separate paired select bit lines and a sense amplifier, and a dummy (n) channel transistor equipped with the same parasitic coupling capacitance. CONSTITUTION:When the data of a memory cell A are read out, a gate signal TG1 is ended and non-selected paired bit lines BL are separated from the sense amplifier. After the fine differential signals of the paired bit lines BL are transmitted to N1 and N2 points, a gate signal TG0 is ended and (n) channel transistors 100 and 101 are cut off. Then, the select bit line is separated from the sense amplifier. Simultaneously, the signal TG0 is activated and dummy (n) channel transistors 200 and 201 are turned ON. Thus, the potential of a sense signal is prevented from being lowered by the parasitic coupling capacitance of the transistors 100 and 101, the high data can be amplified at high speed and the access time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic RAM, and particularly to a data sensing method thereof.

[Conventional technology]

Figure 3 is a circuit diagram of a dynamic ROM showing a conventional sense amplifier and memory array configuration. (2
) QO # n-channel μ transistor (3) (4
) An n-channel transistor (7) that transmits the data of a certain sense amplifier and bit line from 19+ to
(8) , N-channel transistor (100) with TGo as the gate signal, (lO1), n-channel transistor (102) with TG1 as the gate signal
l (lω).

The word lines that control the writing of data to the WL memory cell/l/A and the reading of data from the memory ▲, BL, D] are bit line pairs, YFi column address signals, I/O, I/O is a data input/output line pair, So,
S0 is a sense amplifier drive signal.

FIG. 4 is a timing chart of each signal in FIG. 3.

Note that the figure shows the case of reading High data from memory 7 ▲.

Next, a reading operation of data in a memory cell applied to the conventional sense amplifier and memory cell array *a will be described. When reading data from memory cell A/A, first lower the gate signal TG1, and then the transistor (102)
, (1o3), the unselected bit line pair BL, EL is separated from the sense amplifier. Then, word #WL of memory cell lvA is raised. If the bit line pair BL, 1, 2, and 6 (vo. is the power supply voltage) is precharged, and the data of the memory cell /l/A is High, the potential of BL is #f;g▼. Several hundred mV above 0 is b%
In the case of LOWO field 1 +, it drops by several hundred mV. BTJ (-lvc0 - several hundred mV
), the minute difference signal of Ding L (-Too) is Nl, N! After the signal is transmitted to 2, the gate signal TG0 is lowered, transistors (100) and (101) are cut off, and the selected bit line pair is separated.

Here, the drive signal 8. , S0 is activated to operate the sense amplifier, and the potentials of Nl and N2 are amplified to Ov, the power supply voltage, and! Data is transmitted to the line pair 0/0 through transistors (7) and 8, which are turned on at the rising edge of the signal.

In this way, the conventional sensing method reduces the capacitance during sensing to Nl, N2 by separating the bit line pair during sensing.
The capacitance is reduced to a minute point.

This allows for faster sensing operations, ie, shorter access times.

However, due to disconnection of the selected bit line, the gate signal fTGo
When turning down (TG1), transistor (100)
(101) or transistor/ (102) (10
3) There is a problem that the potentials at the Nl and N2 points also drop due to the O parasitic coupling capacitance. The drop in sense signal potential is High
This results in a large loss during data amplification, and becomes a major hindrance to shortening access time.

[WlI1 to be solved by the invention] In the conventional sense amplifier and memory cell array structure, when separating the bit line pair and the sense amplifier in order to reduce the load capacitance during sensing, a transformer 7 agate transistor is used for separating the bit line pair and the sense amplifier. There is a problem in that the sense signal voltage decreases due to parasitic coupling capacitance due to the applied clock.

The present invention was made to solve the above-mentioned problems, and an object thereof is to obtain a dynamic RAM that prevents the sense signal potential from decreasing and shortens the access time.

(Means for solving ml!) The dynamic RAM according to the present invention has, in addition to a transformer 7 agate transistor that separates a sense amplifier and a bit pair, a transformer 7 agate transistor that has the same parasitic coupling capacity as this transformer 77 gate transistor. N-channel transistors are provided on both sides of a sense amplifier.

[Effect]

The dynamic RAM according to the present invention can shorten the access time by providing a dummy n-channel ρ transistor. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
The figure is a circuit diagram of a dynamic RA 1 showing the sense amplifier and memory cell array configuration of the present invention. I died in the figure,
A certain memory cell lvA1 p-channel transistor (
1) (2) α0, n-channel transistor (3)
(4) +91 to warn the seven power amplifiers, bit line Bt
, UY to the I/O line.
), TGj as the gate signal -1n: n-channel tongistor (lO2) (l03), negative phase of TG0, dummy h-channel tongistor (lO2) (l03) with TGj as gate signal (20
0) (201), T (h negative phase, 1 n-channel transistor (gog) with TT1 as the gate signal
(2o3). and n-channel μtotunster (100) (1Dl) (102) (10
3) (200) (goyu) (go2) (203)
The parasitic coupling capacitance of is exactly the same.

, wb is a word line that controls writing of data to memory cell/kA and reading of data from memory 7μ▲, BL and l are bit line pairs, Y is a column address signal,
Engineering/op Engineering/0 is data input/output line pair % SO l
Mo is a sense amplifier drive signal.

FIG. 2 is a timing chart of each signal in FIG. 1.

Note that FIG. 2 shows the case of reading Hogh data from the memory cell fi/A.

Next, the operation will be explained.

When reading the data in memory 7A/A, use the bits of the gate 1L and BL of the non-release furnace.
, are separated from the sense amplifier, and the bit line pair BL, T'
After the L minute difference signal is transmitted to the N1 and li2 points, the gate signal TO is transmitted. is turned off, and the n-channel transistor (1
00), (10e) to disconnect the selected bit line and the sense amplifier, and at the same time cut off the gate signal T.
Launched G, and became a fan on the N channel (!
! 00) Turn on (!!01) 0 By doing this, the drop in the sense signal potential due to the parasitic coupling capacitance of the transistor (100) (m1) is prevented, high data can be amplified at high speed, and the access time is shortened. be done.

〔Effect of the invention〕

As described above, according to the present invention, since a dummy n-channel transistor having the same parasitic coupling capacitance as the transformer 7 agate transistor which disconnects and separates the selected bit line pair and the sense amplifier is provided, high speed operation can be achieved without lowering the sense signal potential. This has the effect of being able to be amplified by a sense amplifier.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a dynamic RAM showing a sense amplifier and memory cell array structure according to an embodiment of the present invention;
Fig. 2 is a timing chart of each signal in Fig. 1, Fig. 3 is a circuit diagram of a conventional sense amplifier and a timer access RAM showing a memory cell array configuration, and Fig. 4 is a timing chart of each signal in Fig. 3. It is. In the figure, (1) (2) GO are p, channeled transistors constituting the sense amplifier, (3) (4) (
91 is an n-channel fungistor that constitutes a sense amplifier; (5) and (6) are n-channel fungistors and capacitors that each make up 7μ of memory; (7) and (8) are bit line data processors/0. L-channel transistors, (100), (101), (102)
, (103) is an rrf channel transistor, (2
00) , (20l) , (202) , (20
3) is a tammy n-channel transistor. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a dynamic RAM having a configuration in which one sense amplifier is provided for two bit line pairs, each bit line pair on both sides of the sense amplifier includes an n-channel transistor for isolating the sense amplifier and the bit line pair; Dummy n with the same parasitic coupling capacitance as the transistor
A dynamic RAM characterized by having a channel transistor.