JPS6270445U - - Google Patents
Info
- Publication number
- JPS6270445U JPS6270445U JP1985162182U JP16218285U JPS6270445U JP S6270445 U JPS6270445 U JP S6270445U JP 1985162182 U JP1985162182 U JP 1985162182U JP 16218285 U JP16218285 U JP 16218285U JP S6270445 U JPS6270445 U JP S6270445U
- Authority
- JP
- Japan
- Prior art keywords
- back surface
- external lead
- lead terminals
- board
- extended
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims 1
- 239000008188 pellet Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
第１図は本考案の一実施例の断面図、第２図は
従来例の断面図である。 １，１′……配線基板、２……金属パターン（
裏面）、３，３′……外部リード端子、４……半
田、５……ペレツトコート樹脂、６……ＩＣペレ
ツト、７……端子、８，８′……基板裏面取付部
分。
従来例の断面図である。 １，１′……配線基板、２……金属パターン（
裏面）、３，３′……外部リード端子、４……半
田、５……ペレツトコート樹脂、６……ＩＣペレ
ツト、７……端子、８，８′……基板裏面取付部
分。
Claims (1)
- 配線基板裏面に、外部リード端子にそれぞれ対
応した分離領域を有する金属パターンを設け、前
記外部リード端子の基板裏面取付部分を延長して
、前記金属パターンにそれぞれ連結していること
を特徴とする混成集積回路装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985162182U JPS6270445U (ja) | 1985-10-22 | 1985-10-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985162182U JPS6270445U (ja) | 1985-10-22 | 1985-10-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6270445U true JPS6270445U (ja) | 1987-05-02 |
Family
ID=31089201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985162182U Pending JPS6270445U (ja) | 1985-10-22 | 1985-10-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6270445U (ja) |
-
1985
- 1985-10-22 JP JP1985162182U patent/JPS6270445U/ja active Pending