JPS6266646A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce wiring capacity by forming wirings of a multilayer structure in the step of an insulating film and a through hole portion, and of a single layer structure in the flat portion to prevent the wirings from being stepwisely disconnected. CONSTITUTION:Polysilicon wirings 12 and then selectively N<+> type source and drain are formed through a gate oxide film on a P-type Si substrate 11, and a P<+> type substrate connecting layer 13 is formed. An SiO2 film 14 is accumulated, and a window 15 is opened. Then, an aluminum film 16, an MoSi film 17 are superposed by sputtering to form a wiring pattern 18. A resist mask 19 is coated to isotropically etch the film 17 with CF4+O2 gas. The mask 19 is removed, an SiO2 film 20 is superposed, selectively opened, and aluminum wirings 21 are attached to complete an FET. According to this configuration, the wirings 18' of 2-layer of the films 16, 17 in the film 14 and of single layer of the film 16 in other flat portion are formed on the window 15 and the wirings 12, the film 17 prevents the wirings 18' from being stepwisely disconnected in the step on the window 15 and the wirings 12 to reduce wiring capacity, thereby accelerating the operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor substrate 48, and particularly improves the formation of wiring.

[Technical background of the invention]

As is well known, conventional wiring techniques are mostly At single-layer wiring, but various types of laminated wiring are also known. For example, as laminated wiring, two-layer wiring consisting of a polycrystalline silicon layer (lower layer)/a refractory metal silicide layer (upper layer), or a two-layer wiring consisting of a titanium layer (lower layer)/At layer (upper layer), etc. are known. ing. Here, in the former case, the refractory metal silicide layer exists to lower the resistance of the polycrystalline silicon layer. On the other hand, in the latter case, the titanium layer exists in order to prevent At from entering the silicon substrate or St from entering the red layer in the silicon substrate, or to reduce the contact resistance between the At layer and the substrate.

[Problems with background technology]

However, the conventional technology has the following problems.

That is, wiring including At has a capacitance with its surroundings, which impedes signal transmission through the wiring and reduces the operating speed of the LSI. This wiring capacitance includes a capacitance 31"1 between the bottom surface of the wiring 1 and the silicon substrate 2, as shown in FIG.
% Capacity RCz between side surface of wiring 1 and silicon substrate 2, wiring 1
, 1 there is a capacitance C3 between them. Note that 3 is a 5i02 film. On the other hand, although the wiring width has been reduced with the miniaturization of elements, the wiring thickness and wiring length have not been reduced. The former is because the influence of open wiring defects, electromigration, etc. is taken into account, and the overall film thickness is determined at locations where the wiring film thickness is thin at contact holes and step portions. Moreover, the latter is associated with an increase in element density. By the way, among the three capacitances C1, C3, and C3, only C1 decreases as the element becomes smaller, and C2
does not decrease. On the contrary, C3 rapidly increases as the wiring space becomes finer. Therefore, the total wiring capacitance increases with miniaturization, which becomes an obstacle to increasing the speed of the device.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce wiring capacitance and increase the speed of element operation while avoiding defects such as disconnection of wiring. .

[Summary of the invention]

The present invention provides wiring with a multilayer structure in the stepped portions and contact hole portions of an insulating film provided on a semiconductor substrate, and a single layer structure in other flat portions, and breaks in the wiring at the stepped portions. The main idea is to avoid such defects as well as to reduce wiring capacitance and increase the speed of operation of the device.

In the present invention, examples of the stepped portion include wiring made of polycrystalline silicon buried in the insulating film.

[Embodiments of the invention]

Hereinafter, a MOS transistor according to an embodiment of the present invention will be described in order of manufacturing steps with reference to FIGS. 1(-) to 1(d).

(1) First, an element region was formed on a P-type silicon substrate 11, and then a gate electrode (not shown) made of polycrystalline silicon was formed via a gate oxide film. At the same time, a wiring 12 made of polycrystalline silicon (hereinafter referred to as poly wiring) was formed.

Next, highly concentrated arsenic and boron are ion-implanted into the substrate 11 using a resist as a mask, and annealing is performed to form N+ type source/drain regions (none of which are shown), as well as contact with the substrate 1. Therefore, a P-type diffusion layer 13 was formed. Next, a 1 μm thick layer of 5
After depositing the 102 film Z4, the StO
□The entire film 14 was removed to form a contact hole 15. Next, an At layer 16 with a thickness of 3000× was formed on the entire surface by sputtering, and then a molybdenum silicide (MoSi) layer 17 with a thickness of 500× was formed by sputtering. Furthermore, the MoSi layer 17 and the At layer 16 were selectively removed at the same time to form a two-layer wiring I8 (first
Figure (11) shown).

(2) Next, a resist 19 was formed on the Mo11 layer 17 corresponding to the diffusion layer 13 and the poly wiring 12, that is, on a portion with a step on the base. Next, using this resist 19 as a mask, the Mo51 layer 17 is coated with CF4+02.
Isotropic dry etching was performed using the same gas. This results in
Only the parts covered by resist 19 are At@16 and Mo
A wiring 18' having a structure of 51 layers, 1702 layers, and a single layer structure of an At layer 16 was formed in the portion not covered with the resist 19 (as shown in FIG. 1(b)). Next, the resist 19 was peeled off (as shown in FIG. 1(c)). Furthermore, after depositing a 5tO2 film 20 with a thickness of 1.5 μm as an interlayer insulating film on the entire surface, through holes (not shown) were formed. Thereafter, a 1 μm thick red coating was deposited on the entire surface and patterned to form a second layer of At wiring 21, thereby manufacturing a MOS transistor (as shown in FIG. 1(d)).

As shown in FIG. 1(d), the MOS transistor according to the present invention has an At layer 16 and an M
The structure has a two-layer structure of the oSi layer I7 and a single-layer structure of the At layer 16 with wiring 18' in the other flat portion. Therefore, according to the present invention, the presence of the Mo81 layer 17 at the contact hole 15 portion and the stepped portion where the polyline wire 12 is present can prevent the interconnection 1B' from breaking, and reduce the capacitance of the interconnection 18'. The device can operate at high speed.

In fact, according to the present invention, the thickness of the wiring 18' on the flat part can be reduced from the conventional 1 μm to 3000X (
(See Figure 3). Therefore, the aforementioned capacity tCx can be reduced to about half, and C3 can be reduced to about 1/3. Therefore, even if the wiring spacing becomes small, the wiring capacitance does not increase much in the prior art as shown in FIG. Further, as shown in FIG. 6, when design rules are plotted on the horizontal axis, the conventional technology has a large wiring capacitance and the device speed does not improve much, whereas the present invention dramatically improves the speed.

On the other hand, in terms of the reliability of the wiring 1B', as shown in FIG.
By leaving the o51 layer, breakage can be prevented.

Furthermore, according to the present invention, by isotropically etching the upper Mo81 layer 17, a sharp step difference is reduced, and the 5102 film 2
It is also possible to prevent disconnection of wiring in two or more layers separated by 0.

In the above embodiment, a case has been described in which the wiring 18' has a two-layer structure of the MoSi layer and the M layer in the contact hole portion and the stepped portion, but the structure is not limited to this, and may have a structure of three or more layers.

Further, in the above embodiment, after forming the wiring 18 having a two-layer (Mo81 layer and At layer) structure, the Mo11 layer in the flat part was selectively removed to form the wiring @xs', but the present invention is not limited to this. . For example, after selectively removing the Mo11 layer in the flat part,
The wiring 18' may be formed by selectively removing the two layers at the same time.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a semiconductor device that can prevent disconnection of wiring at contact hole portions and step portions, reduce wiring capacitance, and achieve high-speed operation of elements.

[Brief explanation of the drawing]

FIGS. 1(,) to (d) show a MOS according to an embodiment of the present invention.
2 is a cross-sectional view of a semiconductor device for explaining wiring capacitance according to the prior art; FIG. 3 is a cross-sectional view of a semiconductor device for explaining wiring capacitance according to the present invention; FIG. FIG. 4 is a pattern plan view of a semiconductor device according to the present invention, FIG. 5 is a characteristic diagram showing the relationship between wiring capacitance and wiring spacing, and FIG. 6 is a characteristic diagram showing the relationship between speed and design rule. 11... P-type silicon substrate, 12... Poly wiring,
14.20...SiO□ film, 15...Contact hole, I6...AtI@, 17...MoSi R,
1g + 18'... wiring, 21... At wiring. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 1 Figure 3 Dimensions Figure 5

Claims (1)

[Claims] It comprises a semiconductor substrate, an insulating film provided on the semiconductor substrate and having at least one of a step portion or a contact hole, and a wiring provided on the insulating film, wherein the wiring is connected to the step portion and the contact hole of the insulating film. A semiconductor device characterized by having a multilayer structure in a contact hole portion and a single layer structure in other flat portions.