JPS6262555A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which has less irregular electric characteristics by selecting a metal silicide having less layer resistance variation for an impurity for forming a diffused layer, and forming a plurality of silicide layers of different materials on a different conductive type diffused layer. CONSTITUTION:A tungsten silicide film 3 is formed on an N-type diffused layer 2 on the surface of a silicon substrate 1 formed by implanting arsenic and phosphorus, and a titanium silicide film 5 is formed on a P-type diffused layer 4 formed by implanting boron. The layer resistance variations of the both silicide films on the diffused layers can be suppressed to 10% or less in the film 3 on the layer 2, and can be almost eliminated in the film 5 on the layer 4. In other words, the layer resistance of the silicide films can be maintained almost constant irrespective of a method of forming the diffused layer and the silicide film and following heat treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device suitable for improving the controllability of the electrical characteristics of a metal silicide film formed on a diffusion layer. .

[Background of the invention]

Conventionally, a semiconductor device in which a metal silicide layer is formed on the surface of a semiconductor substrate having n-type and p-type impurity diffusion layers,
As described in JP-A No. 60-41259, the structure was such that the same metal silicide layer was formed on both of the diffusion layers. According to this structure, it is possible to reduce the resistance of the junction including both of the above-mentioned scattering layers, and to provide a semiconductor device suitable for high integration. However, during heat treatment after forming the metal silicide layer and both diffusion layers, due to redistribution of the n-type and p-type impurities, the above-mentioned impurities are diffused into the metal silicide layer, and each of the above-mentioned diffusion layers is There was a problem in that the layer resistances of the metal silicide layers had different values. For example, when arsenic diffuses into a titanium silicide film,
Although the layer resistance increases, the layer resistance hardly changes even if boron is diffused. In addition, in the case of tungsten silicide films, arsenic diffusion can suppress the increase in layer resistance to some extent;
The layer resistance increases by about twice as much due to boron diffusion. Furthermore, these increases in layer resistance cause greater non-uniformity due to the amount of impurity diffusion into the silicide film. Such non-uniformity in layer resistance causes non-uniformity in the electrical characteristics of the semiconductor device, and becomes a major problem in highly integrated semiconductor devices.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned problems of the conventional semiconductor device, and even if the formation and post-formation treatment of a metal silicide layer and a diffusion layer are performed under different conditions, immediately after formation and after undergoing post-formation treatment, Another object of the present invention is to provide a semiconductor device with less variation in layer resistance of the metal silicide layer and with good controllability of electrical characteristics.

[Summary of the invention]

In order to achieve the above object, the present invention provides a structure for a semiconductor device in which the layer resistance fluctuation of a metal silicide film is not affected by the introduction of impurities or the treatment after the formation of the silicide. The outline of the present invention will be explained using FIG. 1 and FIG. 2.

In FIG. 1, a tungsten silicide film 3 is formed on an n-type diffusion layer 2 on the surface of a silicon substrate 1 formed by introducing arsenic and phosphorus, and a tungsten silicide film 3 is formed on an n-type diffusion layer 2 formed by introducing boron.
The structure is such that a titanium silicide film 5 is formed on a type diffusion layer 4. Here, when a titanium silicide film is formed on the n-type diffusion layer 2, although there are differences depending on the method of forming the n-type diffusion layer and the method of forming the titanium silicide film, when a subsequent heat treatment is applied, the titanium silicide film becomes Due to the diffusion of n-type impurities into the titanium silicide film, the layer resistance of the titanium silicide film increases by about 50% at most compared to the case where no impurities are introduced. Similarly, when a tungsten silicide film is formed on the p-type diffusion layer 4, the layer resistance of the tungsten silicide film is up to 1o○% compared to the case without impurity introduction.
Rise.

Therefore, the layer resistance of the titanium silicide film on the n-diffusion layer is
It has a maximum non-uniformity of 50%, and the layer resistance of the tungsten silicide film of the p-type diffusion layer has a maximum non-uniformity of 100%. However, in the present invention, the layer resistance fluctuation of both silicide films on each diffusion layer can be suppressed to about 10% or less by the tungsten silicide film 3 on the n-type diffusion layer 2, and It can be almost eliminated by the upper titanium silicide film 5. In other words,
The layer resistance of each silicide film can be kept almost constant regardless of the method of forming each diffusion layer and silicide film, and regardless of the subsequent heat treatment.

Next, as shown in FIG. 2, metal silicides made of different materials are provided on a predetermined diffusion layer 7 of the silicon substrate 6 (a).
. Here, the first silicide film 8 is made of titanium silicide, and the second silicide film 9 is made of tungsten silicide. Next, contact holes 11 are formed in the phosphor glass film 1o by dry etching in order to form electrodes and wiring on predetermined diffusion layers 7 (b). After that, the surface is cleaned with an HF-based etching solution for electrode/wiring formation soap to form the electrode/wiring (C). In such a process, the first silicide film 8 is The second silicide film 9 serves to keep the layer resistance low, and the second silicide film 9 serves to prevent the first silicide film 8 from being attacked by the dry etching and the HF-based etching.

In addition, in FIG. 2, when the first silicide film 8 is made of tungsten silicide and the second silicide film 9 is made of titanium silicide, the first silicide lE[
8 serves to reduce layer resistance fluctuations when the diffusion layer 7 is an n-type diffusion layer, and the second silicide film 9
When the electrode wiring 11 is made of aluminum, it serves as a barrier metal for the first silicide film 8.

As described above, the present invention selects a metal silicide with small layer resistance fluctuation for the impurity constituting the diffusion layer, and forms a plurality of silicide layers of different materials on the diffusion layers of different conductivity types. Accordingly, a semiconductor device with less variation in electrical characteristics can be realized. In addition, when a metal silicide layer is provided between the diffusion layer and the electrode/wiring, by configuring it with multiple silicide layers with different materials and characteristics, it is possible to realize a manufacturing process that takes advantage of the characteristics of each silicide layer, which improves reproducibility and A highly reliable semiconductor device can be realized.

[Embodiments of the Invention] Examples of the present invention will be described below with reference to FIGS. 3 and 4.

[Example 1] Production of CMOS transistor As shown in FIG. 3(a), a field oxide film 13 with a film thickness of 500 nm, P Type-filled diffusion layer 14, surface concentration is I
A p-well diffusion layer 15 with a junction depth of 3 μm, a gate oxide film 16 with a thickness of 20 nm, a polycrystalline silicon film 17 doped with phosphorus with a thickness of 400 nm, and a silicon film with a thickness of 30 nm. An oxide film 18 was formed.

Next, after forming a titanium metal film 19 with a thickness of 50 nm over the entire surface, the titanium metal film 19 was left only in the transistor portion where the n-type silicon substrate surface was exposed, and the remaining portion was removed. Thereafter, a silicon oxide film 20 is formed only on the titanium metal film 19, and a tungsten metal film 20 is formed only on the p-well diffusion layer 15 by selective CVD.
1 was formed to a thickness of 50 nm (b).

Next, a titanium silicide film 22 and a tungsten silicide film 23 are formed in a self-aligned manner by heat treatment at 650° C. for 30 minutes in a hydrogen atmosphere, and the silicon oxide film 20 and unreacted titanium metal film and tungsten metal film are removed. After removal, heat treatment at 900°C, 20°C in an argon atmosphere.
Heat treatment was performed for a few seconds, and boron 2 was added to the transistor part on the left in the same figure.
4 with an implant energy of 30 keV I x 1010
Ions are implanted by /ad to form the titanium silicide film 2.
A boron ion implantation layer 25 was formed under the tungsten silicide film 23, and arsenic 26 was ion-implanted into the tungsten silicide film 23 by LX 1016/cxl at an implantation energy of 150 keV into the transistor portion shown in the figure. c). At this time, the film thicknesses of the titanium silicide film 22 and the tungsten silicide film 23 are each 110 mm.
They were about 0n and 120nm.

After that, after depositing a PSG film 27 (film thickness 400 nm), heat treatment is performed at 1000°C for 20 seconds in a nitrogen atmosphere to diffuse p+ diffusion M28 under the titanium silicide film 22 and n0 diffusion under the tungsten silicide film 23. Layer 29 was formed (d).

Furthermore, after processing the PSG film 28 and making contact holes, aluminum electrodes and interconnections 30 were formed (e).

According to this example, it is possible to form a silicide film that has approximately the same resistance as titanium silicide and tungsten silicide, and furthermore, even if any heat treatment is performed before forming aluminum electrodes and wiring, the layer resistance of each silicide film can be reduced to 1. It was possible to maintain the resistance at 5Ω/mouth and 5Ω/mouth.

Therefore, the variation in resistance of the source/drain regions of each MOS transistor can be almost ignored, and the reliability of the highly integrated CMO5-LSI has been significantly improved. Furthermore, the degree of freedom in the LSI manufacturing process after forming the silicide film has also been improved.

[Example 2]...Production of MOS transistor Fig. 4 (
As shown in a), on the n-type silicon substrate 31 used in Example 1, a field oxide film 32 with a thickness of 500 nm, a gate oxide film 33 with a thickness of 20 nm are formed. After forming a phosphorus-doped polycrystalline silicon film 34 with a thickness of 400 nm, a P- diffusion layer 35 with a junction depth of 0.3 μm is formed, then a sidewall (silicon oxide film) 36 is formed, and then a junction is formed. A p'' diffusion layer 37 having a depth of 0.2 μm was formed. Here, the P− and P+ diffusion layers were formed by boron diffusion.

Next, the p″″ diffusion layer 37 and the polycrystalline silicon film 3 are
4, in a self-aligned manner, a titanium silicide film 38 of about 1
Then, a tungsten silicide film 39 was formed to a thickness of 30 nm (c).

Thereafter, a PSA film (film thickness: 40 nm) 40 was deposited, contact holes were formed by photolithography and dry etching, and after pre-cleaning with an HF-based etching solution, aluminum electrodes and interconnections 41 were formed (d).

According to this embodiment, the titanium silicide film
Since the resistance of the drain region and gate region is kept low, and the titanium silicide is not attacked by the dry etching or HF etching due to the tungsten silicide film, a MOS transistor with good device characteristics and high reliability can be constructed.

Also, the steps for forming the titanium silicide film and the tungsten silicide film described in this embodiment were reversed.

Titanium silicide film/tungsten silicide film/P+
After configuring the diffusion layer/p-diffusion layer, heat treatment is performed in a nitrogen atmosphere to convert the titanium silicide film into a titanium nitride film, thereby forming a titanium nitride film/tungsten silicide film that has barrier properties against aluminum electrode formation. Since this can be easily carried out, the device fabrication process after forming the silicide film becomes extremely simple.

〔Effect of the invention〕

According to the present invention, even if heat treatment or other treatments are performed after the silicide film is formed, the electrical characteristics such as the layer resistance of the silicide film immediately after the silicide film is formed can be maintained well, so that highly integrated semiconductors can be used. It is effective in improving the reliability and controllability of the device. Furthermore, since it is not affected by the process after forming the silicide film, the degree of freedom in the semiconductor device manufacturing process is significantly improved.

[Brief explanation of the drawing]

FIGS. 1 and 2 are cross-sectional views of a semiconductor device for explaining the present invention in detail, and FIGS. 3 and 4 are process diagrams in which the present invention is applied to fabricate a MoS transistor.

Claims (1)

[Claims] A semiconductor device having a p-type impurity diffusion layer and an n-type impurity diffusion layer, characterized in that a plurality of metal silicide layers of different materials are provided on each of the diffusion layers.