KR100344218B1 - Method for fabricating heavily doped well of semiconductor device - Google Patents
Method for fabricating heavily doped well of semiconductor device Download PDFInfo
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- KR100344218B1 KR100344218B1 KR1019950030040A KR19950030040A KR100344218B1 KR 100344218 B1 KR100344218 B1 KR 100344218B1 KR 1019950030040 A KR1019950030040 A KR 1019950030040A KR 19950030040 A KR19950030040 A KR 19950030040A KR 100344218 B1 KR100344218 B1 KR 100344218B1
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Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로 특히 전력MOS소자나 IGBT와 같이 고농도와 저농도의 이중 웰을 갖는 반도체 장치의 고농도 웰 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a high concentration well of a semiconductor device having a double well of high concentration and low concentration, such as a power MOS device or an IGBT.
일반적으로 IGBT나 전력MOSFET의 재조공정에서 VF, dV/dt 특성을 만족시키기 위하여 고농도의 웰(well)이 필요하다. VDD구조의 경우 고농도의 웰은 문턱전압의 상승을 초래하므로 월 내에 선택적으로 고농도의 도우핑을 시키게 되는데, 이때 필연적으로 마스크(MASK)를 사용하게 된다.In general, high concentration wells are required to satisfy the VF and dV / dt characteristics in the manufacturing process of IGBTs or power MOSFETs. In the case of the VDD structure, a well of high concentration causes a rise of a threshold voltage, thereby selectively doping a high concentration within a month. In this case, a mask is inevitably used.
제1도는 종래의 고농도웰 제조방법에 의하여 만들어진 전력 MOS소자의 단면도이다.1 is a cross-sectional view of a power MOS device made by a conventional high concentration well manufacturing method.
소정의 반도체기판(1)상에 소자간의 절연을 위한 절연영역을 형성한 후 게이트 산화막과 다결정실리콘막(3)을 순차적으로 형성한다. 그다음 상기 다결정실리콘막의 소정영역을 식각한 후 붕소로 이온주입공정을 실시하여 저농도의 P웰(5)을 형성한다. 그다음 고농도의 P웰을 형성하기 위한 마스크를 형성한 후 이온주입공정을 실시하여 고농도의 P웰(7)을 형성한다. 그다음 소오스영역을 형성하기 위한 마스크를 형성한 후 비소로 이온주입공정을 실시하여 소오스영역(9)을 형성한다. 그다음 PSG(Phosrous Silicide Gless)막(11)과 금속층(13)온 형성한다.After forming an insulating region for insulation between devices on a predetermined semiconductor substrate 1, a gate oxide film and a polysilicon film 3 are sequentially formed. Then, after etching a predetermined region of the polysilicon film, an ion implantation process is performed with boron to form a low concentration P well 5. Next, after forming a mask for forming a high concentration P well, an ion implantation process is performed to form a high concentration P well 7. Next, after forming a mask for forming the source region, an ion implantation process is performed with arsenic to form the source region 9. Then, a PSG (Phosrous Silicide Gless) film 11 and a metal layer 13 are formed.
상술한 설명에서 알 수 있는 바와 같이 고농도의 P웰을 형성하기 위하여 별도의 마스크가 사용되므로 공정이 길어져서 제조의 공기가 길어지고, 고농도 웰 형성시으 이온주입공정으로 문턱전압값이 변화한다는 문제점이 있었다.As can be seen from the above description, since a separate mask is used to form a high concentration P-well, the process is lengthened, resulting in a long manufacturing process, and a threshold voltage change in the ion implantation process during the formation of a high concentration well. There was this.
따라서 본 발명의 목적은 MOS 소자의 제조방법에 있어서 문턱전압값에 영향을 주지 않을뿐만 아니라 별도의 마스크를 사용하지 않고 고농도의 P 웰을 형성하는 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a manufacturing method for forming a high concentration P well without using a mask, as well as not affecting the threshold voltage value in the manufacturing method of the MOS device.
상기한 바와 같은 본 발명의 목적을 달성하기 위하여 제1 이온주입공정에 의하여 제1도전형의 저농도 웰이 형성된 소정의 반도체 기판상애 상기 제1 이온주입공정보다 높은 에너지로 제1도전형을 고농도로 이온주입하는 제2 이온주입주입공정과, 상기 저농도 웰 상에 엑티브영역을 형성하기 위한 마스크를 형성한 후 제2도전형의 이온을 주입하는 제3 이온주입공정과, 층간절연막율 증착 및 리플로우(reflow)하는 공정을 순차 적으로 구비하여, 상기 리플로우공정시 제2 이온주입공정에 의한 제1 도전형 영역과 제3 이온주입공정에 의한 제2 도전형 영역이 동시에 후확산(drive-in)되도록 함으로써, 상기 제1도전형과 제2도전형의 확산계수의 차이를 이용하여 제2도전형의 액티브영역과 제1도전형의 고농도 웰을 동시에 형성함을 특징으로 한다.In order to achieve the object of the present invention as described above, a high concentration of the first conductivity type is achieved at a higher energy than the first ion implantation process on a predetermined semiconductor substrate on which a low concentration well of the first conductivity type is formed by the first ion implantation process. A second ion implantation process for implanting ions, a third ion implantation process for implanting ions of a second conductivity type after forming a mask for forming an active region on the low concentration well, interlayer dielectric film deposition and reflow and a step of sequentially reflowing so that the first conductivity type region by the second ion implantation process and the second conductivity type region by the third ion implantation process are simultaneously driven-in during the reflow process. By using the difference between the diffusion coefficients of the first conductive type and the second conductive type, the active region of the second conductive type and the high concentration well of the first conductive type are simultaneously formed.
이하 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 MOS소자의 단면도이고, 제3(A)-(C)도는 본 발명에 따른 제조공정도이다.2 is a cross-sectional view of the MOS device according to the present invention, and FIGS. 3A to 3C are manufacturing process drawings according to the present invention.
상기 제3(A)도에서 소정의 반도체 기판(21) 상에 다결정실리콘막(23)을 증착한 후 소정영역을 식각하여 소정 농도의 붕소로 제1 이온주입공정을 실시함으로써 상기 기판내에 저농도의 P웰(25)을 형성한다. 그다음 소정농도의 붕소로 제2 이온주입공정을 실시한다. 이때 이온주입에너지는 100Kev 이상의 고에너지를 사용한다.In FIG. 3A, a polysilicon film 23 is deposited on a predetermined semiconductor substrate 21, and then a predetermined region is etched to perform a first ion implantation process with boron of a predetermined concentration. P well 25 is formed. Then, a second ion implantation step is performed with boron at a predetermined concentration. At this time, the ion implantation energy uses a high energy of 100Kev or more.
그다음 상기 제3(B)도에서 상기 기판상에 포토레지스트를 도포하여 액티브영역 형성을 위한 마스크(27)를 형성한 후 비소로 제3 이온주입공정을 실시한다.Then, in FIG. 3B, a photoresist is applied on the substrate to form a mask 27 for forming an active region, and then a third ion implantation process is performed with arsenic.
그다음 상기 제3(C)도에서 상기 마스크(27)를 제거한 후 기판(21)상에 PSG막(29)을 도포한 후 리플로우(reflow) 시킨다. 그러면 상기 제2 및 제3 이온주입공정에서 주입된 붕소이온과 비소이온이 동시에 후확산되면서, 두 이온의 확산계수의 차이로 인하여 소오스영역(31)과 고농도의 P웰(33)이 동시에 형성된다.Next, after removing the mask 27 in FIG. 3C, the PSG film 29 is coated on the substrate 21 and then reflowed. Then, as the boron ions and the arsenic ions implanted in the second and third ion implantation processes are simultaneously diffused, the source region 31 and the high concentration P well 33 are simultaneously formed due to the difference in the diffusion coefficient of the two ions. .
그다음 금속층을 증착하여 배선(35)을 형성하면 상기 제2도에 도시된 바와 같은 반도체소자가 완성된다.Then, the wiring 35 is formed by depositing a metal layer, thereby completing a semiconductor device as shown in FIG.
본 발명의 일실시예에서는 N 채널을 갖는 전력MOS소자에 대하여 설명하였으나 다른 실시예에서는 P채널을 갖는 전력MOS소자나 IGBT제조시에도 적용할 수 있다.While an embodiment of the present invention has described a power MOS device having an N channel, other embodiments may be applied to the manufacture of a power MOS device having an P channel or an IGBT.
상술한 바와 같이 본 발명은 VDD구조를 갖는 반도체소자애 있어서 고농도 웰을 만들때 별도의 마스크를 사용하지 않고 저농도의 제1 이온주입공정으로 P웰을 형성한 후 이어서 고농도 P웰을 위한 제2 이온주입공정을 실시한 다음 액티브영역을 위한 제3 이온주입공정을 실시하여 상기 제2 및 제3 이온주입공정에 의한 이온을 동시에 후확산 시킴으로써 고농도의 P웰과 액티브 영역을 동시애 형성할 수 있다. 이에따라 따스크공정을 한공정 줄일 수 있는 효과가 있으며, 고농도웰이 기판내의 소정깊이에서 형성되도록 제2 이온주입공정을 고에너지로 실시하여 기판표면의 불순물농도에는 영향을 미치지 않음으로써 안정된 문턱전압을 확보할 수 있는 효과도 있다.As described above, in the semiconductor device having a VDD structure, a P well is formed by a low concentration first ion implantation process without using a mask when making a high concentration well, and then a second ion for a high concentration P well is used. After the implantation process, a third ion implantation process for the active region may be performed to simultaneously post-diffusion the ions obtained by the second and third ion implantation processes, thereby simultaneously forming a high concentration of the P well and the active region. As a result, it is possible to reduce the Dask process by one step, and the second ion implantation process is performed at a high energy so that a high concentration well is formed at a predetermined depth in the substrate, thereby not affecting the impurity concentration on the substrate surface. There is also an effect that can be secured.
제 1 도 종래의 반도체 장치의 단면도1 is a cross-sectional view of a conventional semiconductor device
제 2 도 본 발명에 따른 반도체 장치의 단면도2 is a cross-sectional view of a semiconductor device according to the present invention
제 3 도 본 발명에 따른 반도체 장치의 제조방법3 is a method of manufacturing a semiconductor device according to the present invention
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| KR1019950030040A KR100344218B1 (en) | 1995-09-14 | 1995-09-14 | Method for fabricating heavily doped well of semiconductor device |
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| KR1019950030040A KR100344218B1 (en) | 1995-09-14 | 1995-09-14 | Method for fabricating heavily doped well of semiconductor device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5715458A (en) * | 1980-07-02 | 1982-01-26 | Hitachi Ltd | Manufacture of semiconductor device |
| US4562638A (en) * | 1983-11-09 | 1986-01-07 | Siemens Aktiengesellschaft | Method for the simultaneous manufacture of fast short channel and voltage-stable MOS transistors in VLSI circuits |
| JPS6142163A (en) * | 1984-08-04 | 1986-02-28 | Sharp Corp | Manufacture of semiconductor device |
| JPH02296342A (en) * | 1989-05-10 | 1990-12-06 | Fuji Electric Co Ltd | Manufacture of mosfet |
| US5071777A (en) * | 1987-08-18 | 1991-12-10 | Deutsche Itt Industries Gmbh | Method of fabricating implanted wells and islands of cmos circuits |
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- 1995-09-14 KR KR1019950030040A patent/KR100344218B1/en active IP Right Grant
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5715458A (en) * | 1980-07-02 | 1982-01-26 | Hitachi Ltd | Manufacture of semiconductor device |
| US4562638A (en) * | 1983-11-09 | 1986-01-07 | Siemens Aktiengesellschaft | Method for the simultaneous manufacture of fast short channel and voltage-stable MOS transistors in VLSI circuits |
| JPS6142163A (en) * | 1984-08-04 | 1986-02-28 | Sharp Corp | Manufacture of semiconductor device |
| US5071777A (en) * | 1987-08-18 | 1991-12-10 | Deutsche Itt Industries Gmbh | Method of fabricating implanted wells and islands of cmos circuits |
| JPH02296342A (en) * | 1989-05-10 | 1990-12-06 | Fuji Electric Co Ltd | Manufacture of mosfet |
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