JPS6262452U - - Google Patents

Info

Publication number
JPS6262452U
JPS6262452U JP15313985U JP15313985U JPS6262452U JP S6262452 U JPS6262452 U JP S6262452U JP 15313985 U JP15313985 U JP 15313985U JP 15313985 U JP15313985 U JP 15313985U JP S6262452 U JPS6262452 U JP S6262452U
Authority
JP
Japan
Prior art keywords
semiconductor substrate
microstrip line
elements
mmic
ground conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15313985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15313985U priority Critical patent/JPS6262452U/ja
Publication of JPS6262452U publication Critical patent/JPS6262452U/ja
Pending legal-status Critical Current

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  • Waveguides (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aは本考案のMMICの一実施例を示す
単極双投MMICスイツチの平面パターン図、第
1図bは第1図aのX―X′から見た断面図であ
り電気力線の状態を示す図、第2図aは本考案の
MMICの他の実施例を示す単極双投MMICス
イツチの平面パターン図、第2図bは第2図aの
X―X′から見た断面図であり電気力線の状態を
示す図、第3図aは本考案のMMICの他の実施
例を示す多段増幅器のMMICの平面パターン図
、第3図bは第3図aのX―X′から見た断面図
であり電気力線の状態を示す図、第4図a,b及
び第5図a,bは従来の単極双投MMICの平面
パターン図及び電気力線の状態を示す断面図であ
る。 11…接地導体膜、12…半導体基板、16―
a,16―b…マイクロストリツプ線路、17…
誘電体膜、18…金属膜。
FIG. 1a is a plan pattern diagram of a single-pole double-throw MMIC switch showing an embodiment of the MMIC of the present invention, and FIG. 1b is a cross-sectional view taken along line X-X' in FIG. Figure 2a is a plan pattern diagram of a single pole double throw MMIC switch showing another embodiment of the MMIC of the present invention, Figure 2b is a view taken from X-X' in Figure 2a. FIG. 3a is a cross-sectional view showing the state of electric lines of force, FIG. 3a is a plane pattern diagram of a multi-stage amplifier MMIC showing another embodiment of the MMIC of the present invention, and FIG. 3b is a diagram showing the state of the lines of electric force. 4a, b and 5 a, b are cross-sectional views seen from X', showing the state of the lines of electric force. FIG. 11... Ground conductor film, 12... Semiconductor substrate, 16-
a, 16-b...Microstrip line, 17...
Dielectric film, 18...metal film.

Claims (1)

【実用新案登録請求の範囲】 一方の面に接地導体膜が形成された半導体基板
と、 この半導体基板の他方の面に形成された複数の
素子と、 この複数の素子を相互に接続するマイクロスト
リツプ線路と、 このマイクロストリツプ線路の中の所定のマイ
クロストリツプ線路上を横断して設けられ、前記
半導体基板上に形成された誘電体膜と、この誘電
体膜上に形成された前記マイクロストリツプ線路
を覆う金属膜とを具備したことを特徴とするモノ
リシツクマイクロ波集積回路装置。
[Claims for Utility Model Registration] A semiconductor substrate with a ground conductor film formed on one surface, a plurality of elements formed on the other side of the semiconductor substrate, and a microstructure interconnecting the plurality of elements. a dielectric film provided across a predetermined microstrip line in the microstrip line and formed on the semiconductor substrate; A monolithic microwave integrated circuit device comprising: a metal film covering the microstrip line.
JP15313985U 1985-10-08 1985-10-08 Pending JPS6262452U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15313985U JPS6262452U (en) 1985-10-08 1985-10-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15313985U JPS6262452U (en) 1985-10-08 1985-10-08

Publications (1)

Publication Number Publication Date
JPS6262452U true JPS6262452U (en) 1987-04-17

Family

ID=31071757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15313985U Pending JPS6262452U (en) 1985-10-08 1985-10-08

Country Status (1)

Country Link
JP (1) JPS6262452U (en)

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