JPS61104602U - - Google Patents
Info
- Publication number
- JPS61104602U JPS61104602U JP18901784U JP18901784U JPS61104602U JP S61104602 U JPS61104602 U JP S61104602U JP 18901784 U JP18901784 U JP 18901784U JP 18901784 U JP18901784 U JP 18901784U JP S61104602 U JPS61104602 U JP S61104602U
- Authority
- JP
- Japan
- Prior art keywords
- dielectric substrate
- electrical components
- hole
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 3
- 230000000149 penetrating effect Effects 0.000 claims 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Waveguide Connection Structure (AREA)
- Waveguides (AREA)
Description
第１図はこの考案の一実施例によるハイブリツ
ド集積回路を示す斜視図および断面図、第２図お
よび第３図はそれぞれ従来のハイブリツド集積回
路を示す斜視図および断面図である。
図中、１は誘電体基板、２は金属パターン、３
は金属製キヤリア、４は電気部品、５は貫通孔で
ある。なお、図中同一符号は同一、又は相当部分
を示す。
FIG. 1 is a perspective view and a sectional view of a hybrid integrated circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are a perspective view and a sectional view of a conventional hybrid integrated circuit, respectively. In the figure, 1 is a dielectric substrate, 2 is a metal pattern, and 3 is a dielectric substrate.
4 is a metal carrier, 4 is an electric component, and 5 is a through hole. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
形成され、電気部品が載置される誘電体基板、こ
の誘電体基板の裏面側に接合して設けられた金属
製キヤリア（地導体）、上記電気部品の接地パタ
ーン予定領域に設けられ上記誘電体基板を貫通す
る貫通孔を備え、上記貫通孔の孔壁に導電物を付
着形成したことを特徴としたハイブリツド集積回
路。 A dielectric substrate on which a conductor pattern constituting an electric circuit is formed and on which electrical components are placed, a metal carrier (ground conductor) bonded to the back side of this dielectric substrate, and the electrical components mentioned above. What is claimed is: 1. A hybrid integrated circuit comprising a through hole provided in a planned grounding pattern area and penetrating the dielectric substrate, and a conductive material is adhered and formed on a wall of the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18901784U JPS61104602U (en) | 1984-12-13 | 1984-12-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18901784U JPS61104602U (en) | 1984-12-13 | 1984-12-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61104602U true JPS61104602U (en) | 1986-07-03 |
Family
ID=30746476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18901784U Pending JPS61104602U (en) | 1984-12-13 | 1984-12-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61104602U (en) |
-
1984
- 1984-12-13 JP JP18901784U patent/JPS61104602U/ja active Pending