JPS626186A - Inspecting device for logical circuit - Google Patents

Abstract

PURPOSE:To obtain an inspecting device of a logical circuit which can extract a delay failure, by setting the time for observing an output of a circuit to be inspected, by a test unit and also pin unit. CONSTITUTION:The titled device is constituted of a block 1 for providing an inspecting input, a circuit to be inspected 2, a coincidence detecting circuit 3 and memory devices 4, 5. In the memory device 4, the observation time of an output pin is stored at every inspecting input train. In the memory device 5, an output expected value of every inspecting input train is stored. An output of the circuit to be inspected 2 is compared with the output expected value of the memory device 5 in the coincidence detecting circuit 3 by the observation time of the memory device 4. In this way, by comparing the output of the circuit to be inspected 2 with the output expected value by an optional observation time at every inspecting input train, a delay failure of a logical circuit can be extracted.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a method for testing logic circuits.

In particular, the present invention relates to a logic circuit testing device suitable for identifying defects in delay lines.

[Background of the invention]

A conventional logic circuit testing apparatus, for example, as shown in the GR1792 tester, is capable of changing the output observation time of the circuit under test on a test-by-test basis. Testing was possible when the output of the circuit under test reached a stable state after applying a test input string from this button. However, since it is not possible to switch to the output unit of the circuit, no consideration has been given to extracting defects in the delay line.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic circuit testing device that can detect delays by setting the time for observing the output of a circuit under test on a test-by-test basis and on a pin-by-pin basis.

[Summary of the invention]

The feature of the present invention is that the expected output value of the circuit under test corresponding to the test input string and the observation time corresponding to the output pin are stored in the storage device, and the output observation time of the circuit under test can be changed on a pin-by-pin basis. be.

[Embodiments of the invention]

An embodiment of the present invention is shown below in Figures 1 and 2.

This will be explained with reference to FIG.

FIG. 1 shows a logic circuit testing device according to the present invention, in which a program 1. Circuit under test 2
．． It is composed of a match detection circuit 3 and storage devices 4 and 5. The observation time of the output pin is stored in the storage device 4 for each test input column as shown in FIG. The storage device 5 stores expected output values for each test input string as shown in FIG.

The output of the circuit under test 2 is compared with the expected output value of the storage device 5 at the observation time of the storage device 4 in the coincidence detection circuit 3. As described above, according to this embodiment, by comparing the output of the circuit under test 2 with the expected output value at an arbitrary time and sub-time for each test input string, the delay quality of the logic circuit is determined as shown in FIG. It has the effect of being removed.

〔Effect of the invention〕

According to the present invention, the output of the circuit under test can be compared with the expected output value at any observation time for each test input string, so by setting the observation time and the expected output value in accordance with the characteristics of the logic circuit. This has the effect of extracting delays in logic circuits.

[Brief explanation of drawings]

FIG. 1 is a diagram of a test device for a logic circuit according to an embodiment of the present invention;
@Figure 2 is a display diagram showing the output observation time for each inspection input column,
FIG. 3 is a display diagram showing expected output values for each test input string, and FIG. 4 is a time chart of the circuit of FIG. 1. 1...Inspection input string block. 2...Circuit under test, 3...-Several circuits. 4.5...Storage device. 6.7.8...Output of the circuit under test.

Claims (1)

[Claims] 1. In a device that tests a circuit under test by applying a test input string to the circuit under test and comparing this output with an expected output value of the circuit under test stored in advance in a storage device, 1. A logic circuit testing device characterized by comprising means for setting circuit output observation time on a test-by-test basis and on a pin-by-pin basis.