JPS6060571A - Inspecting device for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To measure a work current through simple constitution by selecting an external terminal which functions as the output terminal of a test step by an information processing function, and turning off a switch connected thereto. CONSTITUTION:An input test pattern outputted by a pattern formatter PT controlled by a CPU is supplied fixedly in an optional test step. Pattern of registers for bits corresponding to external terminals of the formatter PT is read out to select an external terminal corresponding to logic 1, and the corresponding switch of an interface INF is turned off. Consequently, the external terminal which functions as the output terminal increases in impedance and no current is supplied to a measurement system. When the current flowing from a source voltage supply terminal is measured by a measuring unit DC in said state, only a leak current different from the test item of a function test which flows to CMOSLCDUT to be inspected is measured through the simple constitution.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a testing device for semiconductor integrated circuits, and for example, to a technology effective for testing device for current consumption of 0MO3 (complementary metal-insulator semiconductor). .

[Technical background]

In a CMO3 integrated circuit device, one of the inspection items is to measure the current (leak current) flowing from the power supply voltage terminal.

This inspection item has the following problems. That is, when the output terminal is connected to the measurement system, current flows from the output terminal to the measurement system. For this reason, even if the current flowing from the power supply terminal is measured, the current flowing through the measurement system is included, and therefore it is not possible to accurately identify the current flowing only through the CMO3 circuit.

Therefore, it is conceivable to disconnect all external terminals from the tester and measure the above current. However, in this case, there is a problem in that the input terminal is in a floating state and the input level is at an intermediate level, resulting in a large through current.

It is also conceivable to examine test patterns in advance and disconnect those that will become output terminals under a specific test pattern. However, in this case, only the test patterns known in advance can be applied, and C
In MO3 integrated circuits, a problem arises in that it is necessary to examine each test pattern.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit testing device that can measure leakage current using a simple method.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the tester is equipped with a function to identify which external terminal has an output function among the original external terminals of a certain test pattern, and when measuring leakage current, the tester disconnects the output terminal from the tester. It is.

〔Example〕

A block diagram of an embodiment of the invention is shown in the drawings.

The device to be tested DUT (CMO3 integrated circuit) is subjected to various functional tests including measurement of its leakage current using the following tester (inspection equipment W). This functional test is a test to check that a logic circuit incorporated as a semiconductor integrated circuit operates as expected. In order to perform such a functional test, input cover turns are added based on the truth table of the device under test DUT, and it is checked whether the expected output signal is being output. For such functional tests, although not particularly limited, the central processing unit CPU
The information processing to form the above-mentioned cover turn signal is performed by the following steps. The actual input pattern is formed by the pattern formatter PT controlled by the central processing unit CPU. The test pattern signal thus formed is then supplied to the device under test D UT via the interface INF. The output signal is transmitted to the measurement unit (DC current measurement unit 7 is shown as a representative in the figure), DC or pattern format PT through the interface INF.
be taken in. Although not shown, it includes a memory device for storing a program for processing information such as the test pattern signal, or for holding captured data and expected values.

In this embodiment, although not particularly limited, the pattern formatter PT is provided with a bit register corresponding to the external terminal of the device under test DUT, and the corresponding terminal is used as an input terminal according to the input pattern signal formed above. Information on whether it functions or functions as an output terminal is written. For example, when using a certain terminal as an input terminal, the contents of the corresponding register are set to logic "0", and when used as an output terminal, the bit of the corresponding register is set to logic "1". It is.

Writing a pip pattern to such a register is as follows:
The test pattern is formed by referring to the test pattern signal in the test step, and is performed every time each input pattern signal is formed.

Note that in a CMOS gate array, a certain external terminal is selectively used as both an input terminal or an output terminal, so each test step is performed as described above to determine whether the external terminal is an input terminal or an output terminal. This is to identify whether it is functioning as such.

By equipping the tester with such a function, the leakage current can be measured as follows.

That is, in any test step, the person's cover is fixedly supplied. Then, read the bit pattern of the above register, select the terminal whose content is logic "1", and select the terminal that corresponds to the interface I.
The switch means in the NF is turned off. In this state, the external terminal functioning as an output terminal is in a high impedance state and does not supply current to the measurement system. Further, specific input signals are supplied to each input terminal. Therefore, under this condition, the current flowing from the power supply voltage supply terminal is measured by the measuring unit D.
By measuring with C, only the leakage current flowing through the 0M03 circuit can be measured.

Although not particularly limited, it is desirable that the test step for measuring the leakage current be the final test step. This is because the above-mentioned functional test and leakage current measurement are different test items.

〔effect〕

(1) By recording the status of external terminals for each test step, it is possible to automatically disconnect only some terminals from the measurement system when measuring leakage current. This ensures that no current flows from the output terminal to the measurement system.Also, by fixing the input cover turn in the test step, zero current flows from the output terminal to the measurement system.
No through current occurs in the M03 circuit. Therefore, by measuring the current flowing from the power supply terminal in this state, only the leakage current flowing to the 0M03 circuit can be reduced.
This has the advantage that it is possible to set the

(2) By using a simple circuit that stores the state of the external terminal at each test step in a register, it is possible to measure leakage current for any CMO3 integrated circuit at any test step.

(3) According to fl) above, even if the test pattern is automated, the state of the external terminal can be automatically known following it. Therefore, by applying the present invention to a tester having such an automatic test pattern generation capability of 1M, it is possible to automate the measurement of leakage current of a CMO3 integrated circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, any device may be used to generate the test pattern. Further, the circuit for storing the state of the external terminal may utilize a RAM (Random Access Memory) or the like.

Furthermore, in addition to functional tests, the tests include DC tests (input leakage current, withstand voltage, output level).

This is a test that checks whether the power supply current is within the specified range) and AC test (a test that measures switching characteristics such as logic circuit delay time and output signal rise/fall time) functions. may be added.

[Application field]

This invention can be widely used as a testing device for CMO3 integrated circuit devices.

[Brief explanation of the drawing]

The drawing shows a professional computer 1 showing an embodiment of the present invention. DUT...Device under test (CMOS bond circuit), INF...
・Interface, PT...Nomata format, CPU...Central processing unit, DC...Measurement unit

Claims (1)

[Claims] 1. A function for forming a test pattern signal for performing a functional test, an information processing function for selecting an external terminal to function as an output terminal from among external terminals in an arbitrary test step, and a CMO3s product circuit to be tested. a switch function for selectively connecting the device and the tester, and turning off a switch means connected to a terminal functioning as an output terminal according to the information processing under the test step;
A semiconductor integrated circuit testing device characterized by having a measurement function for measuring a current flowing from a power supply terminal of a CMO3 integrated circuit to be tested. 2. The semiconductor integrated circuit testing device according to claim 1, wherein the CMO3 integrated circuit device to be tested is constituted by a gate array formed by a master slicing method. 3. The information processing function for selecting one of the external terminals that functions as an output terminal is constituted by a register that stores the states of all external terminals. 2. The semiconductor integrated circuit testing device according to item 2.