JPS6261322A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6261322A JPS6261322A JP19940785A JP19940785A JPS6261322A JP S6261322 A JPS6261322 A JP S6261322A JP 19940785 A JP19940785 A JP 19940785A JP 19940785 A JP19940785 A JP 19940785A JP S6261322 A JPS6261322 A JP S6261322A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- phosphorus
- epitaxial layer
- low concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置の製造方法に関し、詳しくした中性
子照射を用いた核変換により不純物を生成し、これを拡
散源として用いる半導体装置の製造方法に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a semiconductor device in which impurities are generated through nuclear transmutation using neutron irradiation and the impurities are used as a diffusion source. .
従来の半導体装置の製造において、低濃度の不純物拡散
層はイオン打込み法により形成されていた。しかしなが
ら、通常のイオン打込み法では。In the conventional manufacturing of semiconductor devices, low concentration impurity diffusion layers have been formed by ion implantation. However, in the normal ion implantation method.
表面に凹凸のある構造に、均一な不純物拡散層を形成す
る事は不可能である。例えば第2図に示したような、半
導体基板1に溝2を形成した構造において、該溝2の側
壁部3に、不純物を制御してドープする事は、従来のイ
オン打込み法では勿論、熱拡散法によっても工学的に極
めて困難であった。It is impossible to form a uniform impurity diffusion layer in a structure with an uneven surface. For example, in a structure in which a groove 2 is formed in a semiconductor substrate 1 as shown in FIG. 2, it is possible to dope the side wall 3 of the groove 2 with controlled impurities using conventional ion implantation methods as well as heat treatment. The diffusion method was also extremely difficult from an engineering perspective.
本発明の目的は、上記従来の技術では工学的に不可能で
あった低濃度拡散層の、複雑な構造への形成を可能にす
る手段を提供することである。An object of the present invention is to provide a means that makes it possible to form a low-concentration diffusion layer into a complex structure, which has been impossible in terms of engineering with the above-mentioned conventional techniques.
上記目的を達成するため本発明は、中性子による核変換
反応例えば
を利用して低濃度の不純物を形成し、これを拡散源とし
て低濃度不純物拡v層を形成するものである。即ち第1
図(a)に示したように、シリコン基板4上に、エピタ
キシャル層5を形成するに当り、原料ガスとして30S
iを50%含有したモノシラン(SiH4)を用いると
、該基板4中には、天然のアイソトープ比である4%し
か”Sjが含まれていないのに対し、該エピタキシャル
層5中には50%の”Siが含まれる。これに中性子n
を照射すると、式1に示した反応でリン(P)が、該基
板4中には1.01sロー3の濃度に生成し、一方該エ
ビタキシャル層5中には10”cm−’生ずる。In order to achieve the above object, the present invention forms a low concentration impurity using, for example, a nuclear transmutation reaction using neutrons, and uses this as a diffusion source to form a low concentration impurity expansion layer. That is, the first
As shown in Figure (a), when forming an epitaxial layer 5 on a silicon substrate 4, 30S is used as a raw material gas.
When monosilane (SiH4) containing 50% i is used, the substrate 4 contains only 4% of the natural isotope ratio, whereas the epitaxial layer 5 contains 50% "Si" is included. In this, neutron n
When irradiated with , phosphorus (P) is generated in the substrate 4 at a concentration of 1.01 s rho3, while in the epitaxial layer 5 at a concentration of 10''cm-'.
その後、n照射に伴う結晶欠陥のアニールのため、窒素
雰囲気中で1100’l’r、3時間の熱処理を加える
事により、第1図(b)に示すように、基板4中にエピ
タキシャル層からPが拡散され低濃度P拡散層6を形成
する。Thereafter, in order to anneal the crystal defects caused by the n-irradiation, heat treatment is applied for 3 hours at 1100'l'r in a nitrogen atmosphere, so that the epitaxial layer is removed from the substrate 4 as shown in FIG. 1(b). P is diffused to form a low concentration P diffusion layer 6.
以」二本発明の詳細な説明した如く1本発明によれば核
変換を利用する事により、低濃度の不純物拡散層を、十
分制御して形成する事が可能である。As described in detail below, according to the present invention, by utilizing nuclear transmutation, it is possible to form a low concentration impurity diffusion layer with sufficient control.
以下本発明を、実施例に基づき詳細に説明する。 The present invention will be described in detail below based on examples.
実施例 1
本実施例では、CVD法により絶縁膜を形成し、該絶縁
膜すがら不純物を拡散する方法について示す。Example 1 This example shows a method of forming an insulating film by the CVD method and diffusing impurities through the insulating film.
第3図(a)は、P型(100)面、10Ω’Onのシ
リコン基板10に、1f11を形成し、さらにCVD法
により、SiO□層】2を形成した状態を示す。該Si
n2層は50%に30 S i を濃縮したSiH4
を原料ガスとし、酸素02と反応させて堆積した。この
時の成長条件は、温度730℃。FIG. 3(a) shows a state in which 1f11 is formed on a P-type (100) plane, 10Ω'On silicon substrate 10, and an SiO□ layer 2 is further formed by CVD. The Si
The n2 layer is SiH4 with 30 Si concentrated to 50%.
was used as a raw material gas, and was deposited by reacting with oxygen 02. The growth conditions at this time were a temperature of 730°C.
圧力2torr、 S i H4と02の流量比は、1
:20であった。膜厚200n mのS〕02膜を約5
分で堆積できた。Pressure is 2 torr, flow ratio of S i H4 and 02 is 1
:20. The film thickness of 200nm is approximately 5
I was able to deposit it in minutes.
第3図(b)は、該半導体基板に、中性子を照射し、し
かる後tooo℃で10時間アニールを行い。In FIG. 3(b), the semiconductor substrate is irradiated with neutrons, and then annealed at too much degree Celsius for 10 hours.
リン拡散層13を形成した状態を示す。A state in which a phosphorus diffusion layer 13 is formed is shown.
SiO2/Si界面でのリンの偏析係数が約IOである
事からSin、中のリン濃度の約10倍の濃度のリンが
、Si表面に拡散できる。従って、この時のリン拡散層
の表面濃度は約10”’ra−’、一方該半導体基板中
でリン番Sg換された3uSiは、′aJjLが4%で
あるから10”cxn−”台で、基板の比抵抗には全く
影響を与えなかった。Since the segregation coefficient of phosphorus at the SiO2/Si interface is about IO, phosphorus at a concentration about 10 times the phosphorus concentration in the Si can diffuse into the Si surface. Therefore, the surface concentration of the phosphorus diffusion layer at this time is about 10"'ra-', while the phosphorus number Sg-exchanged 3uSi in the semiconductor substrate is on the order of 10"cxn-" since 'aJjL is 4%. , had no effect on the specific resistance of the substrate.
第3図CQ)は、該溝11中のみに不純物拡散を行なう
場合の実施例で、Si基板10と、30Si実質的に含
まない酸化膜14を有する構造において、30Siを5
0%含有する酸化膜12と接しているSi基板中に、リ
ン拡散層13を形成した状態を示す、該リン拡散層13
の接合深さは、中性子照射後の熱処理時間温度に依存す
るため、所望の接合深さの拡散層を形成するには、熱処
理条件を適切に選ぶ必要がある。FIG. 3CQ) is an example in which impurity diffusion is performed only in the groove 11, and in a structure having a Si substrate 10 and an oxide film 14 that does not substantially contain 30Si, 50% of 30Si is
The phosphorus diffusion layer 13 is shown in a state in which the phosphorus diffusion layer 13 is formed in the Si substrate in contact with the oxide film 12 containing 0%.
Since the junction depth depends on the heat treatment time and temperature after neutron irradiation, it is necessary to appropriately select the heat treatment conditions to form a diffusion layer with a desired junction depth.
実施例 2
本実施例では、CVD法により堆積し球Si中からの不
純物拡散に関する方法を示す。Example 2 This example shows a method for diffusing impurities from Si spheres deposited by the CVD method.
第4図(a)は、n型(100)面40Ω・】のSi基
板20上に、エピタキシャル法により、Si単結晶層を
、厚さ3μm堆積した状態を示す。FIG. 4(a) shows a state in which a Si single crystal layer is deposited to a thickness of 3 μm by an epitaxial method on an n-type (100) plane Si substrate 20 of 40Ω.
該単結層の堆積は、SiH4とH2の混合ガスを用い、
1000℃で行った。最初の0.5 μmの厚さの領域
21は、”Siを70%含有するSiH4を用い、その
後、ガスを変え通常のS jH4(” S jを4%含
有)を用いて残りの2.5 μmの膜22を堆積した。The single layer is deposited using a mixed gas of SiH4 and H2,
The temperature was 1000°C. The first 0.5 μm thick region 21 was formed using SiH4 containing 70% Si, and then the remaining 2.5 μm thick was formed using SiH4 containing 70% Si, then changing the gas and using regular S jH4 (containing 4% S j ). A 5 μm film 22 was deposited.
第4図(b)は中性子を照射し。Figure 4(b) shows neutron irradiation.
生成した後、短時間アニール法により、1100℃30
秒間熱処理を行い、中性子照射に伴う結晶損傷を除去す
ると共に、リン拡散層23を形成した状態を示す。この
時の熱処理により、リン拡@層23は、初期状態の厚さ
0.5 μmの該単結晶層21の部分から、該Si基板
20および厚さ2.5μmの該昨結晶層の部分の方向に
、おのおの0.1 μmずつ拡散される。After the formation, short-time annealing is performed at 1100℃30
A heat treatment is performed for a second to remove crystal damage caused by neutron irradiation, and a phosphorus diffusion layer 23 is formed. Due to the heat treatment at this time, the phosphorus expansion layer 23 changes from the initial 0.5 μm thick portion of the single crystal layer 21 to the Si substrate 20 and the 2.5 μm thick portion of the previous crystal layer. The light is diffused by 0.1 μm in each direction.
本実施例で示した如く、本発明によればエピタキシャル
成長用の原料ガス中のアイソトープ濃度を変えるだけで
単結晶中の不純物ドープ分布を変える事が可能であり、
蛇来技術で問題となったオート・ドープ等の不純物濃度
分布制御は容易となる。さらに、本発明によれば、10
1.’aa−3程度の低a度不純物ドープ層を制御され
た状態で精度良く形成する事が可能で特にMO5M型集
積回路の形成に有利である。本実施例では、表面濃度1
×10”an−’t n型埋込み拡散層t ×t o
I G am −3という低濃度の不純物ドープを高精
度で実現出来、この結晶上に形成したMOSトランジス
タのしきい電圧■?□のばらつきを、±10mVと従来
技術の1/4以下に抑える事ができた。As shown in this example, according to the present invention, it is possible to change the impurity doping distribution in a single crystal simply by changing the isotope concentration in the source gas for epitaxial growth.
It becomes easier to control the impurity concentration distribution such as auto-doping, which was a problem with the Jagrai technology. Furthermore, according to the invention, 10
1. It is possible to form a low-a impurity doped layer of about 'aa-3 with high precision in a controlled state, which is particularly advantageous for forming MO5M type integrated circuits. In this example, the surface concentration is 1
×10” an-'t n-type buried diffusion layer t ×t o
Doping with impurities at a low concentration of I G am -3 can be achieved with high precision, and the threshold voltage of a MOS transistor formed on this crystal can be reduced. The variation in □ was suppressed to ±10 mV, less than 1/4 of that of the conventional technology.
」−記説明から明らかなように、本発明によれば、不純
物拡散層を形成する県合、従来技術で問題となった凹凸
のある構造へのドープ、あるいは低濃度の不純物ドープ
層の形成が可能となり、工学的な効果は絶大である。” - As is clear from the description, according to the present invention, it is not possible to form an impurity diffusion layer, dope into an uneven structure that was a problem with the prior art, or form a low concentration impurity doped layer. This has become possible, and the engineering effect is enormous.
第1図は本発明の原理を示す図、第2図は従来技術を示
す図、第3および4図はそれぞれ本発明の異なる実施例
を示す図である。
1.4,10.20・・・シリコン基板、5 H12g
21・・・拡散源、6,13.23・・拡散層。FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing the prior art, and FIGS. 3 and 4 are diagrams showing different embodiments of the present invention. 1.4, 10.20...Silicon substrate, 5 H12g
21...Diffusion source, 6,13.23...Diffusion layer.
Claims (1)
子を含む層を半導体基板上に形成する工程と、該半導体
基板に中性子を照射する工程と、熱処理により該中性子
照射により生じた不純物を該基板あるいは該不純物を含
む層内に拡散し、不純物濃度分布を持つ層を形成する工
程を含むことを特徴とする半導体装置の製造方法。1. A step of forming on a semiconductor substrate a layer containing atoms that are transmuted to produce impurities by neutron irradiation, a step of irradiating the semiconductor substrate with neutrons, and a heat treatment to remove the impurities generated by the neutron irradiation from the substrate. Alternatively, a method for manufacturing a semiconductor device comprising the step of diffusing into a layer containing the impurity to form a layer having an impurity concentration distribution.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19940785A JPS6261322A (en) | 1985-09-11 | 1985-09-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19940785A JPS6261322A (en) | 1985-09-11 | 1985-09-11 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6261322A true JPS6261322A (en) | 1987-03-18 |
Family
ID=16407280
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19940785A Pending JPS6261322A (en) | 1985-09-11 | 1985-09-11 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6261322A (en) |
-
1985
- 1985-09-11 JP JP19940785A patent/JPS6261322A/en active Pending
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