JPH03203229A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03203229A JPH03203229A JP34455289A JP34455289A JPH03203229A JP H03203229 A JPH03203229 A JP H03203229A JP 34455289 A JP34455289 A JP 34455289A JP 34455289 A JP34455289 A JP 34455289A JP H03203229 A JPH03203229 A JP H03203229A
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- heat treatment
- ion
- oxygen
- buried layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 title claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000010438 heat treatment Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims abstract description 14
- 239000007789 gas Substances 0.000 claims abstract description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 239000000203 mixture Substances 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 238000005470 impregnation Methods 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にAsイオン
注入による埋込層形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a buried layer by implanting As ions.
従来、n −typeの埋込層を形成する場合、固相−
固相拡散ソースとしてAsあるいはsb等を含む酸化ケ
イ素を主成分とする塗布液をシリコン基板上に塗布しそ
の後、所望のプロファイルを得るために比較的高温で長
時間の熱処理をし、その後シリコンエピタキシャル成長
させn−typeの埋込層を形成している。Conventionally, when forming an n-type buried layer, a solid phase-
A coating solution mainly composed of silicon oxide containing As or SB as a solid-phase diffusion source is applied onto a silicon substrate, and then heat treatment is performed at a relatively high temperature for a long time to obtain a desired profile, followed by silicon epitaxial growth. An n-type buried layer is formed.
あるいはイオン注入法を用いて埋込層を形成する場合、
シリコン基板に薄い絶縁膜を形成するかもしくは直にシ
リコン基板にAsイオン注入を行ない、その後比較的高
温(〜1150℃)の熱処理を行ない、その後、シリコ
ンエピタキシャル成長させ、n−typeの埋込層を形
成している。Alternatively, when forming a buried layer using ion implantation method,
A thin insulating film is formed on the silicon substrate or As ions are implanted directly into the silicon substrate, followed by heat treatment at a relatively high temperature (~1150°C), followed by silicon epitaxial growth to form an n-type buried layer. is forming.
上述した従来の塗布液を用いて埋込層を形成する場合、
例えば、塗布前処理、塗布液のベーク等の工程数、工程
時間等が多くかかるという欠点がある。また、不純物濃
度のプロファイル制御がイオン注入法に比べ容易でなく
面内均一性が劣るという欠点がある。When forming the embedded layer using the conventional coating liquid mentioned above,
For example, there are disadvantages in that it requires a large number of steps such as pre-coating treatment and baking of the coating solution, and a large amount of process time. In addition, it is difficult to control the impurity concentration profile compared to ion implantation, and the in-plane uniformity is poor.
また従来のイオン注入法ではAsイオン注入後の熱処理
において、熱処理温度が約1150℃のためイオン注入
で生じた結晶欠陥(主にアモルファス層とシリコン結晶
界面の転位等)が十分に回復せず残留欠陥としてデバイ
スに悪影響(電気特性劣下)を与えるという欠点がある
。また熱処理雰囲気が02 / (N 2+O2)>0
.02の場合、酸化性雰囲気が強くなり結晶欠陥(主に
転位)を増長させ、p −n Junctionリーク
を発生させる原因ともなり、デバイスの電気的特性を劣
下させるという欠点がある。In addition, in the conventional ion implantation method, in the heat treatment after As ion implantation, the heat treatment temperature is approximately 1150°C, so crystal defects caused by ion implantation (mainly dislocations at the interface between the amorphous layer and the silicon crystal) are not fully recovered and remain. As a defect, it has the disadvantage of having an adverse effect on the device (deterioration of electrical characteristics). Also, the heat treatment atmosphere is 02/(N2+O2)>0
.. In the case of 02, the oxidizing atmosphere becomes strong, increasing crystal defects (mainly dislocations), causing p-n junction leakage, and deteriorating the electrical characteristics of the device.
本発明のAsイオン注入による埋込層の形成方法は、特
に面方位(111) P−typeシリコン基板を用い
a)、シリコン基板にイオン注入保護膜として絶縁膜
Si○、を形成する事とAsイオン注入後、b)、純粋
な窒素N2と微量の酸素02の混合比が02/ (N2
+O2)−0,02以下のガス雰囲気で1200℃以上
の高温で熱処理を行う事を有している。The method of forming a buried layer by implanting As ions of the present invention uses a (111) P-type silicon substrate in particular. After ion implantation, b), the mixing ratio of pure nitrogen N2 and trace amount of oxygen 02 is 02/(N2
+O2) -0.02 or less gas atmosphere and heat treatment at a high temperature of 1200°C or more.
すなわち、」二連した従来の埋込層形成法に対し、本発
明においては特に面方位(111)、P−typeシリ
コン基板に薄い絶縁膜810.を形成1−1不純SAs
イオンを高ドーズでイオン注入した後、所望のプロファ
イルを得るため、純粋な窒素N。In other words, in contrast to the conventional method of forming two buried layers, the present invention specifically forms a thin insulating film 810. Forming 1-1 impure SAs
After implanting ions at a high dose, pure nitrogen N was used to obtain the desired profile.
と微量の酸素O3の混合比が02/ (N 2 十02
)0.02以下のガス雰囲気中で1200℃以上の温度
で熱処理を行なう。and a trace amount of oxygen O3 at a mixing ratio of 02/(N 2 102
) Heat treatment is performed at a temperature of 1200° C. or higher in a gas atmosphere of 0.02 or lower.
本発明においては、注入ダメージを緩和させるため、シ
リコン基板に薄い絶縁膜Si○2を形成し、不純物As
イオンを高ドーズでイオン注入した後、イオン注入で生
じたアモルファス層とシリコン結晶界面に生じた結晶欠
陥を完全に回復させるために純粋な窒素N2と微量の酸
素02の混合比が02/ (N 2 +O2) = 0
.02以下のガス雰囲気中で1200℃以上で熱処理を
して所望のプロファイルを形成する。In the present invention, in order to alleviate implantation damage, a thin insulating film Si○2 is formed on a silicon substrate, and an impurity As
After ion implantation at a high dose, the mixing ratio of pure nitrogen N2 and a trace amount of oxygen 02 is 02/(N 2 + O2) = 0
.. A desired profile is formed by heat treatment at 1200° C. or higher in a gas atmosphere of 0.02° C. or lower.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)〜(b)は本発明の一実施例の工程断面図
である。FIGS. 1(a) to 1(b) are process cross-sectional views of an embodiment of the present invention.
低濃度P型の面方位(111)を有するシリコン基板1
上全面に、950℃で水蒸気を含む酸化雰囲気でSiO
2膜2をイオン注入保護膜として200人形成した。そ
の後Asイオン3を加速エネルギー70KeV、ドーズ
I X 10 ”atoms/cmlで注入し、純粋な
窒素N2と微量の酸素02の混合比が02/ (N 2
+ 02) = 0.02のガス雰囲気で1200℃
の高温熱処理を40分間行った。従来の技術と比較する
ため、Asイオン注入を5×1015とI X 10
”atoms/cfflの2水準のドーズ量で直に低濃
度P型の面方位(111)を有するシリコン基板上全面
に行い、その後、純粋な窒素N。Silicon substrate 1 with low concentration P type surface orientation (111)
SiO was applied to the entire upper surface in an oxidizing atmosphere containing water vapor at 950°C.
2 Film 2 was used as an ion-implanted protective film for 200 people. Thereafter, As ions 3 were implanted at an acceleration energy of 70 KeV and a dose of I x 10'' atoms/cml, and the mixing ratio of pure nitrogen N2 and a trace amount of oxygen 02 was 02/(N2
+ 02) = 1200℃ in a gas atmosphere of 0.02
A high temperature heat treatment was performed for 40 minutes. For comparison with conventional technology, As ion implantation was performed at 5×1015 and I×10
``It is directly applied to the entire surface of a silicon substrate with a low concentration P type plane orientation (111) at two levels of doses of atoms/cffl, and then pure nitrogen N is applied.
と微量の酸素0□の混合比が02/ (N 2 + 0
2) =0.02のガス雰囲気で1140℃の高温熱処
理を3.5時間行った。但し、熱処理時間は不純物As
の表面濃度、プロファイルを上記1200℃、40分の
プロファイルと同等にするため1140℃3.5時間熱
処理した。The mixing ratio of 0□ and a trace amount of oxygen is 02/(N 2 + 0
2) High temperature heat treatment at 1140° C. was performed for 3.5 hours in a gas atmosphere of =0.02. However, the heat treatment time is
Heat treatment was performed at 1140° C. for 3.5 hours to make the surface concentration and profile equivalent to the profile obtained at 1200° C. for 40 minutes.
さらに上記熱処理を行った後、本発明によるウェル−と
従来の技術によるウェル−に、シリコンエピタキシャル
層5をジクロロシラン(S ]、 H。After further performing the above heat treatment, the silicon epitaxial layer 5 is coated with dichlorosilane (S) and H in the well according to the present invention and the well according to the conventional technique.
Cj22)、塩酸(HCL) 、水素(H2)ガスとド
ピングガスとしてホスフィン(P H8)を湿度108
0℃、真空度80Torrでランプ加熱炉で化学反応さ
せ2.2μm成長させn型埋込層4を形成した。Cj22), hydrochloric acid (HCL), hydrogen (H2) gas and phosphine (PH8) as a doping gas at a humidity of 108
A chemical reaction was carried out in a lamp heating furnace at 0° C. and a vacuum degree of 80 Torr to form an n-type buried layer 4 to a thickness of 2.2 μm.
その後、Wright etch液にシリコンエピタ
キシャル層を形成したウェル−を1分間浸して選択一
エッチを施した後、エッチピットの観察を光学顕微鏡4
00倍で行った。その結果を第2図に示す。After that, the well on which the silicon epitaxial layer was formed was immersed in the Wright etch solution for 1 minute to perform selective etching, and then the etch pits were observed using an optical microscope 4.
It was performed at 00x. The results are shown in FIG.
従来法ではエッチピット密度〜10’ケ/ cnt観察
されたのに対し本発明による埋込層形成法ではエッチピ
ッI・は観察されず本発明の優位性が認められた。In the conventional method, an etch pit density of ~10'/cnt was observed, whereas in the buried layer forming method according to the present invention, no etch pit I was observed, demonstrating the superiority of the present invention.
次に、再び第1図(a)〜(d)を用いて本発明の他の
実施例を説明する。Next, another embodiment of the present invention will be described using FIGS. 1(a) to 1(d) again.
一実施例と同様にして低濃度P型面方位(111)を有
するシリコン基板全面に5iOz膜を形成し、Asイオ
ンを加速エネルギー70 K e Vドーズ、5 X
10 ”atoms/ cn!で純粋な窒素N2と微量
の酸素02の混合比02 / (N 2+O2)=0.
02のガス雰囲気で1200℃の高温熱処理を40分間
行った。従来の技術と比較するため、上記シリコン基板
にSiO2膜を形成しAsイオン注入を加速エネルギー
70KeV、ドーズ5X1015と1x 1016at
oms/c清の2水準で行い、熱処理雰囲気を02/
(N 2 + 02) = 0.02とし、1140℃
3.5時間の高温熱処理を行った。A 5iOz film was formed on the entire surface of a silicon substrate with a low concentration P-type plane orientation (111) in the same manner as in Example 1, and As ions were accelerated at an energy of 70 K e V and a dose of 5.times.
Mixing ratio of pure nitrogen N2 and trace amount of oxygen 02 at 10"atoms/cn! 02/(N2+O2)=0.
A high-temperature heat treatment at 1200° C. was performed for 40 minutes in a gas atmosphere of 0.02. In order to compare with the conventional technology, a SiO2 film was formed on the silicon substrate, and As ions were implanted at an acceleration energy of 70 KeV and a dose of 5 x 1015 and 1 x 1016 at.
The heat treatment was carried out at two levels: oms/c clear, and the heat treatment atmosphere was 02/
(N 2 + 02) = 0.02, 1140°C
High temperature heat treatment was performed for 3.5 hours.
さらに一実施例と同様に1−てそれぞれのウェル−にシ
リコンエピタキシャル層を2.2μm戒長成長n型埋込
層を形成した。Further, in the same manner as in the first embodiment, a silicon epitaxial layer was grown to a length of 2.2 μm to form an n-type buried layer in each well.
その後、一実施例と同様にして、結晶欠陥評価を行った
。その結果を第3図に示す。従来法ではエッチピット密
度が約103ケ/ cnt観察されたのにに対し本発明
による埋込層形成法ではエッチピットは観察されず本発
明の優位性が認められた。Thereafter, crystal defect evaluation was performed in the same manner as in one example. The results are shown in FIG. In the conventional method, an etch pit density of about 103 holes/cnt was observed, whereas in the buried layer forming method according to the present invention, no etch pits were observed, demonstrating the superiority of the present invention.
以上説明したように本発明は、特にP−type面方位
(111)のシリコン基板にイオン注入保護膜として絶
縁膜5iChを形成してAsイオン注入し、注入後純粋
な窒素N2と微量○、の混合比02/ (N 2 +
02) = 0.02以下のガス雰囲気で1200℃の
高温熱処理を行うことにより、イオン注入による損傷を
完全に回復させ、高濃度のn型埋込層を容易に形成でき
る効果がある。As explained above, in the present invention, an insulating film 5iCh is formed as an ion implantation protection film on a silicon substrate with a P-type plane orientation (111), and As ions are implanted, and after the implantation, pure nitrogen N2 and a trace amount of Mixing ratio 02/ (N 2 +
By performing high-temperature heat treatment at 1200° C. in a gas atmosphere of 0.02) = 0.02 or less, damage caused by ion implantation can be completely recovered and a highly concentrated n-type buried layer can be easily formed.
第1図(a)〜(d)は本発明のAsイオン注入による
埋込層形成の一実施例、他の実施例の工程断面図、第2
図、第3図は本発明と従来法による結晶欠陥評価結果を
示す図である。
1・・・・・・シリコン基板、2・・・・・・SiO2
膜、3・・・・・・Asイオン、4・・・・・・n型埋
込層、5・・・・・・エピタキシャル層。FIGS. 1(a) to 1(d) are one embodiment of forming a buried layer by As ion implantation according to the present invention, process sectional views of another embodiment, and a second embodiment of the present invention.
3 are diagrams showing crystal defect evaluation results according to the present invention and the conventional method. 1... Silicon substrate, 2... SiO2
Film, 3... As ion, 4... N-type buried layer, 5... Epitaxial layer.
Claims (2)
化膜を介して不純物を前記シリコン基板の表面にイオン
注入した後、窒素N_2と酸素O_2の混合比がO_2
/(N_2+O_2)=0.02以下のガス雰囲気中で
1200℃以上の温度で熱処理を行い、その後シリコン
エピタキシャル成長を行う工程を有することを特徴とす
る半導体装置の製造方法。(1) After forming a thin oxide film on the surface of a silicon substrate and implanting impurity ions into the surface of the silicon substrate through the oxide film, the mixing ratio of nitrogen N_2 and oxygen O_2 is O_2.
A method for manufacturing a semiconductor device, comprising the steps of performing heat treatment at a temperature of 1200° C. or more in a gas atmosphere of /(N_2+O_2)=0.02 or less, and then performing silicon epitaxial growth.
より高濃度の埋込層領域を形成する半導体装置の製造方
法において、面方位(111)、P−typeシリコン
基板に薄い絶縁膜SiO_2を形成し、不純物Asイオ
ンを高ドーズでイオン注入した後、所望のプロファイル
を得るため純粋な窒素N_2と微量の酸素O_2の混合
比がO_2/(N_2+O_2)=0.02以下のガス
雰囲気中で1200℃以上の温度で熱処理を行い、その
後シリコンエピタキシャル成長を行う工程を特徴とする
半導体装置の製造方法。(2) In a semiconductor device manufacturing method that forms a highly concentrated buried layer region by ion-implanting impurities ^7^5As^+, a thin insulating film SiO_2 is formed on a P-type silicon substrate with a plane orientation of (111). After forming and implanting impurity As ions at a high dose, in order to obtain the desired profile, the mixture ratio of pure nitrogen N_2 and a trace amount of oxygen O_2 is O_2/(N_2+O_2) = 1200 mL or less in a gas atmosphere of 0.02 or less. A method for manufacturing a semiconductor device characterized by a step of performing heat treatment at a temperature of ℃ or higher and then performing silicon epitaxial growth.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34455289A JPH03203229A (en) | 1989-12-28 | 1989-12-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34455289A JPH03203229A (en) | 1989-12-28 | 1989-12-28 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03203229A true JPH03203229A (en) | 1991-09-04 |
Family
ID=18370161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34455289A Pending JPH03203229A (en) | 1989-12-28 | 1989-12-28 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03203229A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121120A (en) * | 1997-08-07 | 2000-09-19 | Nec Corporation | Method for manufacturing semiconductor device capable of flattening surface of selectively-grown silicon layer |
-
1989
- 1989-12-28 JP JP34455289A patent/JPH03203229A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121120A (en) * | 1997-08-07 | 2000-09-19 | Nec Corporation | Method for manufacturing semiconductor device capable of flattening surface of selectively-grown silicon layer |
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