JPS6259410A - Digital graphic equalizer - Google Patents

Abstract

PURPOSE:To prevent intermission of sound and generation of buzz noise by rewriting plural data in response to a designated equalizer characteristic into a coefficient memory from the central coefficient data to the coefficient at both ends or vice versa sequentially. CONSTITUTION:In operating a prescribed switch of a characteristic input section 12, the coefficient data set to coefficient setting sections 6L, 6R is rewritten sequentially at a prescribed period and stored in coefficient memories 13L, 13R of digital signal processors DSPs 3L, 3R. In this case, the coefficient data is rewritten from the central coefficient to the coefficient at both ends or vice versa by using a control signal fed from a CPU 6 and the DSPs 3L, 3R. In setting the equalizer characteristic in this way, the digital sound signal data and the coefficient are multiplied by the DSPs 3L, 3R. The result of arithmetic operation is outputted from a terminal 7 via latch circuits 4L, 4R. Thus, natural aural sense is obtained without intermission of sound or generation of buzz noise.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital graphic equalizer;
The present invention relates to a graphic equalizer that outputs a digital audio signal such as a PCM audio signal by varying the level for each frequency band.

2. Description of the Related Art In recent years, digital signal processors (hereinafter referred to as DSPs)
A digital graphic equalizer has been developed using If a DSP is used, high-speed calculations are possible, and high-precision calculations are also possible due to its extensive multiplication functions.

A conventional digital graphic equalizer using a programmable arithmetic processor such as a DSP changes the entire program or the entire coefficients of a digital filter by, for example, switching pages of memory subsurfaced by the CPU, as the equalizer characteristics are changed. It was designed to be switched at once.

However, in the above-mentioned conventional system, data is initialized when switching programs or coefficients, so data is lost, which causes the sound to be interrupted and create an unnatural sound. Furthermore, since each of the above switching is performed at the same time, a buzz noise is generated, which is unpleasant to the ears. Furthermore, since page switching is performed, the length of the program or the length of the coefficient memory is essentially doubled, which is uneconomical.

Therefore, in order to solve the above-mentioned problem, the present applicant proposed in a patent application dated the same date (title of the invention [Digital Graphic Equalizer]) that a plurality of coefficients of a digital filter are changed at a predetermined period in accordance with the equalizer characteristic variable operation. We proposed a digital graphic equalizer that switches sequentially, does not cause audio interruptions or buzz noise, and requires only a short program and coefficient memory.

Problems to be Solved by the Invention The above proposal is based on the coefficients a1, a2 . ..., when switching a21Il+1 from the value shown in FIG. 4 (A>) to the value shown in FIG. 4 (B), the coefficients a 1 , a 2 , a 3 .
.

al+1. ..., a2Ill+1. However, if the characteristics of both are extremely similar, there is not much of a problem, but if they are not very similar, as shown in (A) and (B) in the same figure, if you switch in the above order, there will be a problem during the switching. At this stage, the coefficient values are not symmetrical with respect to the central coefficient am+1, which means that the transient characteristics until switching becomes unstable, resulting in an unnatural hearing sensation.

The present invention provides a digital
Multiple coefficients of a filter can be switched sequentially from the center to both ends or from both ends to the center at a predetermined period, without causing sound interruptions or buzz noises, and with a short program and coefficient memory. It is an object of the present invention to provide a digital graphic equalizer in which coefficient values become symmetrical in intermediate stages, transient characteristics are stabilized, and a natural hearing sensation is provided.

Means for Solving the Problems In FIG.
Rewritable coefficient memory 13L, 13 corresponding to l+1
Digital signal calculation means for calculating and extracting by the coefficient of R, C
The PU 9, address latch memories 5L and 5R, and coefficient latch circuits 6L and 6R store a plurality of coefficient data in the coefficient memory 13 in accordance with the equalizer characteristics specified by the characteristic input section 12.
These are embodiments of a rewrite control means for sequentially rewriting L and 13R from the center coefficient data to the coefficient data at both ends, or from the coefficient data at both ends to the center coefficient data at a predetermined period.

Operation Corresponding to the equalizer characteristics specified in the characteristic input section 12, a plurality of coefficient data a1 to a21Il+1 are stored in the coefficient memories 13L and 13R from the center coefficient data a to the coefficient data a1 and 82m+1 at both ends, or m+1 or m+1. Coefficient data a1 at both ends. The data is sequentially rewritten from a2ffl+1 to the center coefficient data aIll+1 at a predetermined cycle.

Embodiment FIG. 1 shows a block diagram of an embodiment of the equalizer of the present invention. In the figure, 12 is a characteristic input section, 15 is a display section,
As shown in Fig. 2, the characteristic variable switch sw, 3.5w
2a, swHb, and a flat switch 5Wo1 display element group 151, 152° . . . 15M are provided. 3L and 3R are a DSP for the L channel and a DSP for the R channel, respectively, which perform digital filter calculations in order to realize the equalizer characteristics set in the characteristic input section 12, and internally include coefficient memories 13L, 13R1 program ROM 14L, , 13R, etc.

FIG. 5 shows a concrete block diagram of the DSP3L and 3R. In the figure, a multiplexer (MUX).

Since the program counter (PC), stack, data memory page pointer (DP), auxiliary register, auxiliary register pointer (ARP), shift circuit, etc. are not directly related to the present invention, their explanation will be omitted. DS
P has a multiplier 24 inside as hardware, and its calculation speed reaches about 10 to 100 times that of the CPU. Generally, the calculation by FIR digital filter is 2
There are about 0 to 100 steps, and it must be performed at a sampling period (1/44.1 kl-1z 423us), and high-speed calculation is possible.For example, the SP is a fixed-tap FIR digital system with the configuration shown in Figure 3. It can be effectively used as a filter.

In FIG. 5, a program ROM 14 stores programs executed by the DSP and multiplication coefficients a1 to a.

These data are stored in advance, and are supplied to the controller 27 etc. via the program bus 26, and the multiplier 24 etc. via the program bus 26 and data bus 28. The controller 27 also has an external oscillator (
A clock signal @(CLKIN) is supplied from a source (not shown).

Returning to FIG. 1 again, the same signal processing is performed on the digital audio signals of the L and R channels, so the L channel will be mainly explained. The input terminal 1 is arranged alternately for each sampling period, and the digital audio signal a of each channel of R (Figure 6 (
A)) are supplied to latch circuits 2L and 2R (Fig. 7), while timing controls lc and d (Fig. 7(C) and (D
)) is supplied to the latch circuits 2L and 2R. As a result, the latch circuit 2L (2R) outputs the digital audio signal a to L.
Extracts and outputs only the digital audio signal of the (R) channel.

On the other hand, the interrupt circuits 16L and 16R (Fig. 8) are connected to the DSP3
This is a circuit for setting data transfer timing to L and 3R. That is, DSP3L.

The sampling frequency of the digital audio signal taken into 3R is 44.1 kHz, while DSP3L.

Since the machine cycle of 3R is approximately 20MH2, DSP3L is processed by interrupt circuits 16L and 16R.

DSP3L at a convenient timing for 3R.

Data is being imported into 3R.

The interrupt circuits 16L and 16R are as shown in FIG.
It is composed of a NOR circuit 29 and D flip-flops 30 and 31. Here, a reset signal (R8 signal) generated when a reset switch (not shown) (usually shared with a power switch) is turned on is supplied to one input terminal of the NOR circuit 29 via a terminal 32. be done.

This reset signal is a signal for returning the D flip-flop 30 to its initial state. Further, the other input terminal of the two NOR circuits receives a data enable signal (DEN signal) e as shown in FIG. 6(E) or (F) outputted from the controller 27 shown in FIG. f
is supplied.

The D flip-flop 30 has its data input terminal (D terminal) grounded, and its clear (CL) terminal is supplied with the output signal of the NOR circuit 29. Also, clock (GK)! The signal C or d is supplied to the child. Therefore, the signal C from the Q terminal of the flip-flop 30
Or a signal synchronized with d is output, and the flip-flop 3
1 data input terminal (D terminal).

The D flip-flop 31 receives a clock signal (C
LKOLJT news@) will be provided. Therefore, the I10 branch control signal (BIO signal) output from the Q terminal of the D flip-flop 31 to the controller 27 in the DSPs 3L and 3R is synchronized with the CLKOUT signal, and an interrupt occurs at the falling time of the signal. On the other hand, the 810 signal is reset (ie, becomes high level) at the falling time of the DEN signal.

As shown in FIG. 7, the latch circuits 2L and 2R include D flip-flops FT+ to FII6. It is composed of inverters II and 12 and gate circuits GI+ to Glu. Here, each bit of the 16-bit digital audio signal a supplied from the input terminal 1 is input to the D flip-flop FI.
It is supplied separately to the Di-coupler of +~Fits. On the other hand, the signal @C or d is inputted via the inverter 11 to the respective G terminals of the D flip-flops F[+ to FII6. As a result, the Q output terminal of the D flip-flop FI+ and the F
From the σ output terminals of Iz to F[I6, only the digital audio signal of either the above-mentioned or R channel is extracted and supplied to the input terminals of gate circuits GI+ to GII6.

The DEN signal e or f is supplied as a gate signal to the other input terminal of the gate circuit G (+-GI+s) via the inverter 2. Therefore, the latch circuit 2L to DSP3L
The L channel digital audio signal is output to -
Falling time t3 of the go-go R signal f. At t7, etc., the R channel digital audio signal is output from the latch circuit 2R to the DSP 3R. Note that only the most significant bit (MSB) of the 16-bit digital audio signal is inverted and
is converted to the complement form and output.

The digital audio signal of the L channel is fetched and stored at a predetermined address in the coefficient memory 13 shown in FIG. 5 at time t1. Thereafter, the multiplier 24 uses the digital audio data and the multiplication coefficients a1~ set in the coefficient memory 13.
a, and are multiplied, and the result is the logic operation circuit (ALU) 33 and the accumulator (ACC) 3 shown in FIG.
It is added at step 4.

Next, switching of equalizer characteristics will be explained. When switching the equalizer characteristics, the coefficient data corresponding to the coefficients a1 to ao of the digital filters that substantially constitute the DSPs 3L and 3R are switched, and this switching operation is controlled by the controller 8 (7) CPU 91 'Yes, CPU9, ROMlo,' is configured to operate according to the flowchart shown in FIG. 9 based on control signals from the RAM11.

A case where the equalizer characteristic shown in FIG. 10 is changed from 1 to 2 by operating a predetermined switch of the characteristic input section 12 will be described. The + in the characteristics is the FIR shown in the third diagram.
The coefficients of the digital filter are as shown in FIG. 4 (A), and the characteristics of 2 are as shown in FIG. 4 (B).

Here, the coefficient memory 13L of DSP3L, 3R.

13R is set as shown in FIG. 11, for example, in the operation cycle of the CPU 9, the address latch memory 5L.

5R has address 0.2m+1.1.2m, 2m-1,
... written as 2m+1 (step 1 in Figure 9)
1o), correspondingly, the coefficient latch circuits 6L and 6R have coefficients 81. a21n+1. a2. a2IIl.

a3. a21-1. ..., alIl+1 is in this order r
is written (step 111).

The DSPs 3L and 3R use the latched address data and coefficient data, and store the coefficient memory 13L while the calculation is completed and the next sampling data is received.

Import the coefficient data into 13R. The timing of this acquisition is, for example, every sampling or every two samplings, as long as it is faster than the repetition period of steps 110 to 113 of the CPU 9. Also, address latch memory 5L, 5R
and coefficient latch circuit 6L.

It is also possible to synchronize the writing of 6R with the coefficient data acquisition of DSP3L and 3R.

In this case, in FIG. 12, address latch memory 5
L and 5R are CPU9 and DSP3L.

Control signals supplied from 3R via decoders 36 and 37 control the addresses to be updated in the predetermined order, thereby updating the coefficient data a1 as described above.
．． a2m+1. a2, 82m,...

8m+1 are sequentially rewritten.

This rewriting order is not limited to the above example, but all 'am'8m+2' all
'am+3,''・,82m+1 may be used, or 8m+1, 8m+2.al, a, +3.a, -1,・
....

The order may be a, or all, a,.

aIl+2'8m+3''I-1'am-2'
``'' may also be used, or a1141 ' 8m+
2'aII'am-1'a, a,
...It may be in any order. For example, m÷3m+4 all. 1. ao, all+2. a, al, +3
．． . . . FIG. 4(C) shows the state in the process of being rewritten in the following order. That is, area B is shown in the same figure (A
) from the coefficient data of 1 for the characteristics shown in 11! ! 1(B)
This area has already been rewritten with coefficient data having a characteristic of 2, and areas A+ and Az still have coefficient data having a characteristic of 1.

In this way, the coefficient data a1 to a2IIl+1 are al.

a2. ..., a2ffi+1, but the present invention is characterized in that the coefficients are rewritten sequentially from the center coefficient to the coefficients at both ends, or from the coefficients at both ends to the center coefficient. As a result, as shown in FIG. 4(C), during the rewriting stage, the coefficient values become symmetrical with respect to the central coefficient aI+1, that is, the transient characteristics become stable, resulting in an unnatural hearing sensation. will not be given.

If the sampling frequency is 44.1 kHz, 1 sample is approximately 22.7 m, and 100 samples is 22 m.
．． 7EX 100 = 2.2715, so switching can be performed quickly.

In this case, the flat switch S of the characteristic input section 12
It is detected that Wo (sets the level display to zero) is not pressed (step 100 in Figure 9), and the coefficient setting value in band - (M band configuration from I = 1 to M in Figure 2) is Bands 1 to M are read and the coefficients are rewritten (steps 101 to 104).

Here, when a new operation of the switch sw-swH is detected (step 105), a corresponding coefficient is calculated or selected from the ROM 10 (step 106), and as described above, the coefficient memory 3L,
Coefficients are written to 13R (steps 109 to 113)
). On the other hand, if the flat switch SWo is pressed (steps 100 and 107), the flat coefficient is selected (step 108), and the coefficient memory 3L is
, 13R (steps 109-113).

In this way, when the equalizer characteristic is set in the characteristic input section 12, the coefficients a1 to a2m+1 of the digital filter are sequentially switched at a predetermined period, and the multiplier 24 in 03P3-3R outputs the digital audio signal data and the coefficients a1 to ao.
are multiplied and calculated.

The operation result data is supplied to latch circuits 4L and 4R (FIG. 13). Latch circuits 4L and 4R are output data memory 22L, 22R1 output timing adjustment memory 23L
, 23R. Output data memory 22
As shown in FIG. 13, L is a D flip-flop FL+~
It consists of FLI6 and inverter IL+. Here, each bit of the above 16-bit operation result data is supplied to the Di terminal of the D flip-flop FL+-FL+s, and on the other hand, the GK terminal is supplied from the controller 27 in the DSPaL as shown in FIG. 6(G). The write enable signal (WE multiplied signal g is supplied via the inverter IL+. Therefore, the above operation result data is transferred to the D flip-flops FL+ to FL+ at time t6 when the WE multiplied signal falls.
6 and output from its Q terminal.

Output timing adjustment memory 23LG, t[) flip-flop FOL+ -FOLI6, Invar'1I
It is composed of Lz, TL3, and gate circuits GLt to GL16. Here, the calculation result data is supplied from the Q terminals of the D flip-flops FL+ to FLI6 to the D terminals of the D flip-flops FOL+ to FOL+s. On the other hand, the output timing adjustment pulse b as shown in FIG. 6(B) is supplied to the CK terminals of the D flip-flops FOL+ to FOL+s via the inverter rL2, and is supplied to the CK terminals of the D flip-flops FOL+ to FOL+s via the inverter IL3. It is supplied to one input terminal of GLI6. The above calculation result data i (Fig. 6 (■)) is obtained from the gate circuit GLI ~ The signals are output from the output terminals 7 via the GLIs 6, respectively.

In this way, the DSP3L takes in data at time t1, outputs the calculation result of the previous data at time t2 immediately after that, takes in the next data at the next time t5, and
At the fall time t6 of the E double signal Q, the calculation result of the data taken in at time t1 is written to the output data memory 22, and at the subsequent timing t9 synchronized with the signal a, the calculation result data is transferred from the terminal 7. Output.

On the other hand, the R channel digital audio signal is also processed in the same way as above in the DSP 3R, the output data memory 22R, and the output timing adjustment memory 23R. This operation is easier to understand than the operation of the L channel, so its explanation will be omitted.

FIG. 14 shows a block system diagram of another embodiment of the equalizer of the present invention, in which the same parts as in FIG. 1 are given the same numbers and their explanations will be omitted. This thing's DSP3L'
, 3R' have no coefficient memory internally, but instead have high-speed static RAMs 39L and 39R externally. Address generation circuit (access) 38L and 38R are CP
This is for writing coefficient data from U9 to RAMs 39H and 39R, and as shown in Fig. 15, three-state buffer SL+, decoder DC+, bidirectional buffer SL
It consists of 3. Interface circuits (access) 40L and 40R are DSP3L'.

3R' and the RAMs 39L and 39R for transmitting and receiving signals.As shown in FIG. 15, the three-state buffer SL2, gates G1 to G6,
It is composed of a bidirectional buffer SL4.

This one is a fast static RAM that is a coefficient memory
Since the addresses of 39L and 39R are directly specified from the CPU 9, no interrupt is required compared to the embodiment shown in FIG. 1, and calculations can be made faster accordingly. Coefficient data is stored in RAM39L.

The timing of writing to 39R is the same as in the previous embodiment.

Note that DSP is a programmable digital signal calculation means. This is the i aspect.

Further, the digital filter is not limited to an FIR digital filter, but may be an IIR digital filter or a composite filter of an FIR digital filter and an IIR digital filter.

Furthermore, the channel configuration is not limited to two channels.

In addition, although the digital input and digital output systems have been described, the system is not limited to this.
Of course, by using a D converter and a DA converter for output, an analog input and analog output system can be constructed.

Effects of the Invention According to the digital graphic equalizer of the present invention, a plurality of coefficients of the digital filter are sequentially switched at a predetermined period as the equalizer characteristics are varied.
Compared to conventional systems in which the entire program or coefficients are switched at once by switching pages, there is no interruption in the sound or buzz noise, and a natural hearing sensation can be obtained. Also, the memory for programs and coefficients is short. It is versatile and economical, and furthermore, since the switching of multiple coefficients is rewritten sequentially from the center to both ends or from both ends to the center, the coefficient values become symmetrical during the switching stage, that is, , stable transient characteristics, and the ability to provide a natural hearing sensation.

[Brief explanation of the drawing]

1 and 2 are a block diagram and a schematic diagram of a part thereof of an embodiment of the equalizer of the present invention, respectively, and FIG. 3 is a FIR
A schematic diagram of the digital filter, Figure 4 is a diagram for explaining the coefficients of the FIR digital filter, Figure 5 is a block diagram of the DSP used in the equalizer of the present invention, and Figure 6 is for explaining the operation of the equalizer of the present invention. The flowchart, FIGS. 7 and 8 are specific circuit diagrams of a part of the equalizer of the present invention,
FIG. 9 is a flowchart for explaining the operation of the CPU used in the equalizer of the present invention, FIG. 10 is an equalizer characteristic diagram, and FIG.
The figure shows a memory map of the coefficient memory, FIG. 12 shows a specific block system diagram near the coefficient latch circuit and address latch memory, FIG. 13 shows a specific circuit diagram of a part of the equalizer of the present invention, and FIGS. 14 and 15 show 2A and 2B are block diagrams of other embodiments of the equalizer of the present invention and a specific block diagram of a part thereof, respectively. 1...Digital audio signal input terminal, 2L, 2R. 4L, 4R...Latch circuit, 3L, 3R...DSP
. 5L, 5F? ...address latch memory, 6L, 6R
... Coefficient latch circuit, 7 ... Output terminal, 8 ... Control section, 9 ... CPtJ, 12 ... Characteristic input section, sw
-8WHb. a SWo...Switch, 13L, 13R...Coefficient memo 1c 14L, 14R...Program ROM, 15
...Display section. Patent applicant: Victor Japan Co., Ltd. Figure 3 Figure 4 □. Contain! 1, the coefficient values become symmetrical in the middle of switching, which means that the transient characteristics are stable and a natural hearing sensation can be obtained. 4. Brief description of the drawings FIGS. 1 and 2 are block diagrams and partial schematic diagrams of an embodiment of the equalizer of the present invention, respectively, and FIG. 3 is a FIR
A schematic diagram of the digital filter, Figure 4 is a diagram for explaining the coefficients of the FIR digital filter, Figure 5 is a block diagram of the DSP used in the equalizer of the present invention, and Figure 6 is for explaining the operation of the equalizer of the present invention. The flowchart, FIGS. 7 and 8 are specific circuit diagrams of a part of the equalizer of the present invention,
FIG. 9 is a flowchart for explaining the operation of the CPU used in the equalizer of the present invention, FIG. 10 is an equalizer characteristic diagram, and FIG.
The figure shows a memory map of the coefficient memory, FIG. 12 shows a specific block system diagram near the coefficient latch circuit and address latch memory, FIG. 13 shows a specific circuit diagram of a part of the equalizer of the present invention, and FIGS. 14 and 15 show 2A and 2B are block diagrams of other embodiments of the equalizer of the present invention and a specific block diagram of a part thereof, respectively. 1...Digital audio signal input terminal, 2L, 2R. 4L, 4R...Latch circuit, 3L, 3R...DSP
, 5L, 5R...Address latch memory, 6L, 6R
...Coefficient latch circuit, 7...Output terminal, 8...Control unit, 9...CPU, 12...Characteristics input unit, sw
-swHb. a SWo...Switch, 13L, 13R...Coefficient memory, 14L, 14R...Program ROM, 15...
・Display section. Patent Applicant: Japan Victor Co., Ltd. Figure 15 Procedures...Original Book November 12, 1985 1, Case Description 1985 Patent Application No. 198958 2, Title of Invention Digital Graphic Equalizer 3, Amendments to be made Relationship with the sound incident Patent applicant address 3-12 Moriya-cho, Kanayō-ku, Yokohama, Kanagawa 221 Name (432) Japan Victor Co., Ltd. Representative Director and President Michi Shishi - Department 4, Agent address 102 Chiyoda, Tokyo 5-7 Kojimachi, Figure 10? ! Fl branch (Se) → Fig. 1 Fig. 12 Fig. 14 Fig. 14)?

Claims (5)

[Claims] (1) A characteristic input section for specifying desired equalizer characteristics;
digital signal calculation means for calculating and extracting an incoming digital signal using coefficients of a rewritable coefficient memory corresponding to a plurality of coefficients of the digital filter; A digital device characterized by comprising a rewriting control means for sequentially rewriting the plurality of coefficient data in the coefficient memory from the center coefficient data to the coefficient data at both ends, or from the coefficient data at both ends to the center coefficient data at a predetermined period. -Graphic equalizer. (2) The number of taps of the digital filter is 2_m_+_1
It is an FIR digital filter with symmetrical coefficients, and the plurality of coefficient data are sequentially a_1, a_2 from the input side to the output side.
, a_3..., a_m_+_1,..., a_2_m
Assuming ____1, a_2_m, a_2_m_+_1,
The rewriting order is a_1, a_2_m_+_1, a_
2, a_2_m, a_3, a_2_m_-_1,...
, a_m_+_1, or a_2_m_+_1, a_1
, a_2_m, a_2, a_2_m_-_1, a_3,
..., a_m_+_1, or a_1, a_2_m_
+_1, a_2_m, a_2, a_3, a_2_m_-
_1, ..., a_m_+_1, or a_2_m_+
_1, a_1, a_2, a_2_m, a_2_m_-_
1, a_3, . . . , a_m_+_1. The digital graphic equalizer according to claim 1, wherein: (3) The number of taps of the digital filter is 2_m_+_1
It is an FIR digital filter with symmetrical coefficients, and the plurality of coefficient data are sequentially input from the input side to the output side..., a_m
____1, a_m, a_m_+_1, a_m_+_2,
If a_m_+_3,..., then the rewriting order is
a_m_+_1, a_m, a_m_+_2, a_m_-
_1, a_m_+_3, ... or a_m_+_1
, a_m_+_2, a_m, a_m_+_3, a_m_
-_1, ..., or a_m_+_1, a_m, a_
m_+_2, a_m_+_3, a_m_-_1, a_m
____2, or a_m_+_1, a_m_+_2, a
_m, a_m_-_1, a_m_+_3, . . . The digital graphic equalizer according to claim 1, wherein: (4) The rewriting cycle of the plurality of coefficient data is equal to the sampling cycle of the digital signal input to the digital signal calculation means, and the coefficient memory is rewritten one coefficient data at a time. The digital graphic equalizer according to any one of paragraphs 1 to 3. (5) Any one of claims 1 to 4, wherein the characteristic input section is provided with a switch capable of increasing and attenuating the amplitude for each of a plurality of frequency bands. Digital graphic equalizer as described.